category: Technical Papers

category: Auto, Security & Edge AI

ML for Energy-Performance-Aware Scheduling On Heterogeneous Multicore Architectures (Cambridge)
By Technical Paper Link - 02 Feb, 2026 - Comments: 0

University of Cambridge researchers published "Machine Learning for Energy-Performance-aware Scheduling." Abstract "In the post-Dennard era, optimizing embedded systems requires navigating complex trade-offs between energy efficiency and latency. Traditional heuristic tuning is often inefficient in such high-dimensional, non-smooth landscapes. In this work, we propose a Bayesian Optimizatio... » read more

HW-Triggered Backdoors Across Common GPU Accelerators (BIFOLD, TU Berlin, CISPA)
By Technical Paper Link - 02 Feb, 2026 - Comments: 0

A new technical paper titled "Hardware-Triggered Backdoors" was published by researchers at Berlin Institute for the Foundations of Learning and Data (BIFOLD), TU Berlin and CISPA Helmholtz Center for Information Security. Abstract "Machine learning models are routinely deployed on a wide range of computing hardware. Although such hardware is typically expected to produce identical result... » read more

Chiplet Fundamentals For Engineers: eBook
By Bryon Moyer - 02 Feb, 2026 - Comments: 1

Multi-die assemblies are the next phase of Moore's Law, scaling up and out  to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the individual dies and overall performance increases because a chip is no longer bound by reticle limits. But this is much harder than it sounds. Chiplets don't just snap together like LEGOs, and so... » read more

Benchmark For AI-Aided Chip Design That Evaluates LLMs Across 3 Critical Tasks (UCSD, Columbia)
By Technical Paper Link - 30 Jan, 2026 - Comments: 0

Researchers at UCSD and Columbia University published "ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design." Abstract "While Large Language Models (LLMs) show significant potential in hardware engineering, current benchmarks suffer from saturation and limited task diversity, failing to reflect LLMs' performance in real industrial workflows. To address t... » read more

Impact Of The Film Transfer And Grain Size On The Cu-barrier Properties Of 2D WS2 Films (NUS et al.)
By Technical Paper Link - 29 Jan, 2026 - Comments: 0

A new technical paper titled "Enhancing Cu-barrier properties of 2D-WS2 barriers: The role of grain size and surface passivation" was published by researchers at National University of Singapore, AIXTRON, IMiF and Applied Materials. Abstract "Two-dimensional (2D) films, such as tungsten disulfide (WS2), are being considered by the microelectronics industry as promising barrier and liner s... » read more

Autonomous Driving: Motion Planner Executed on Automotive-Grade Embedded HW (TU Munich)
By Technical Paper Link - 28 Jan, 2026 - Comments: 0

A new technical paper titled "Towards Safe Autonomous Driving: A Real-Time Motion Planning Algorithm on Embedded Hardware" was published by researchers at TU Munich. Abstract "Ensuring the functional safety of Autonomous Vehicles (AVs) requires motion planning modules that not only operate within strict real-time constraints but also maintain controllability in case of system faults. Exis... » read more

Ultra-low-bit LLM Inference Allows AI-PC CPUs And Discrete Client GPUs To Approach High-end GPU-Level (Intel)
By Technical Paper Link - 28 Jan, 2026 - Comments: 0

A new technical paper titled "Pushing the Envelope of LLM Inference on AI-PC and Intel GPUs" was published by researcher at Intel. Abstract "The advent of ultra-low-bit LLM models (1/1.58/2-bit), which match the perplexity and end-task performance of their full-precision counterparts using the same model size, is ushering in a new era of LLM inference for resource-constrained environments... » read more

Semiconductor Supply Chain Security Using Side-Channel Power Measurements and Generative Adversarial Networks (Cornell)
By Technical Paper Link - 26 Jan, 2026 - Comments: 0

A new technical paper titled "Out-of-Band Power Side-Channel Detection for Semiconductor Supply Chain Integrity at Scale" was published by researchers at Cornell University. Abstract "Out-of-band screening of microcontrollers is a major gap in semiconductor supply chain security. High-assurance techniques such as X-ray and destructive reverse engineering are accurate but slow and expensiv... » read more

MFMIS FeTFETs For Energy-Efficient, Scalable CIM Hardware Accelerators (Seoul National University)
By Technical Paper Link - 26 Jan, 2026 - Comments: 0

A new technical titled "Impact of Random Phase Distribution on Ferroelectric Tunnel Field-Effect Transistors With Mitigation Strategies for Compute-in-Memory Applications" was published by researchers at Seoul National University. Abstract "This work presents, for the first time, an investigation of the impact of random phase distribution on ferroelectric (FE) tunnel field-effect transist... » read more

Hypergraph-based Techniques To Map Spiking Neural Networks on Neuromorphic HW (Politecnico di Milano)
By Technical Paper Link - 25 Jan, 2026 - Comments: 0

A new technical paper titled "A Case for Hypergraphs to Model and Map SNNs on Neuromorphic Hardware" was published by researchers at Politecnico di Milano. Abstract "Executing Spiking Neural Networks (SNNs) on neuromorphic hardware poses the problem of mapping neurons to cores. SNNs operate by propagating spikes between neurons that form a graph through synapses. Neuromorphic hardware mimic... » read more

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