A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses


Abstract "RowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (i.e., hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer vulnerability worsens as DRAM cell size and cell-to-cell spacing shrink. Recent studies demonstrate that modern DRAM chips, including chips previously marketed as RowHammer-safe, are even more vulnerable to RowHammer than... » read more

Making BaZrS3 Chalcogenide Perovskite Thin Films by Molecular Beam Epitaxy


Abstract: We demonstrate the making of BaZrS3 thin films by molecular beam epitaxy (MBE). BaZrS3 forms in the orthorhombic distorted-perovskite structure with corner-sharing ZrS6 octahedra. The single-step MBE process results in films smooth on the atomic scale, with near-perfect BaZrS3 stoichiometry and an atomically-sharp interface with the LaAlO3 substrate. The films grow epitaxially via tw... » read more

AKER: A Design and Verification Framework for Safe and Secure SoC Access Control


Abstract: "Modern systems on a chip (SoCs) utilize heterogeneous architectures where multiple IP cores have concurrent access to on-chip shared resources. In security-critical applications, IP cores have different privilege levels for accessing shared resources, which must be regulated by an access control system. AKER is a design and verification framework for SoC access control. AKER builds ... » read more

Dynamic in-chip current distribution simulation technology for power device layout design


Abstract: "This paper reports an in-chip current distribution verification technology for power devices that takes into account the effect of layout parasitics. The proposed method enables verification of dynamic current distribution in a chip considering the influence of layout parasitics from the initial stage of device development by brushing up each element technology of TCAD, Spice mode... » read more

Chip Package Co-design and Physical Verification for Heterogeneous Integration


Abstract: "Physical verification of components in 2.5D and 3D integrated chips is challenging because existing tool flows have evolved from monolithic silicon design. These components are typically designed on separate technology nodes nearly independent of each other and integrated along the design cycle. We developed an integration and verification methodology with a physical design driven... » read more

Simulation-Based Fault Analysis for Resilient System-On-Chip Design


Abstract: "Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover,... » read more

Netlist Decompilation Workflow for Recovered Design Verification, Validation, and Assurance


Abstract: "Over the last few decades, the cost and difficulty of producing integrated circuits at ever shrinking node sizes has vastly increased, resulting in the manufacturing sector moving overseas. Using offshore foundries for chip fabrication, however, introduces new vulnerabilities into the design flow since there is little to no observability into the manufacturing process. At the same ... » read more

A New Multi-Stimuli-Based Simulation Method for ESD Design Verification


Abstract: "This paper analyzes TCAD ESD simulation for both HBM zapping using real-world HBM ESD waveforms as stimuli and TLP testing using square wave TLP pulse trains as stimuli. It concludes that TCAD ESD simulation using either HBM waveforms or TLP pulse trains, alone, is insufficient. We introduce a new mixed-mode simulation flow using combined HBM and TLP stimuli to achieve ESD design pr... » read more

Application and Verification of Effective Heat Spreading Angles on a Multi-Layer Thermal Design


Abstract: "When designing converters, the average junction temperature of the semiconductor is a frequently required estimate. Its analytical calculation requires the total thermal resistance of the cooling arrangement. Unfortunately, due to the complexity of the heat dissipation processes, an estimate of the thermal resistance is usually associated with low accuracy. To significantly improve ... » read more

Quantum well interband semiconductor lasers highly tolerant to dislocations


Abstract "III-V semiconductor lasers integrated on Si-based photonic platforms are eagerly awaited by the industry for mass-scale applications, from interconnect to on-chip sensing. The current understanding is that only quantum dot lasers can reasonably operate at the high dislocation densities generated by the III-V-on-Si heteroepitaxy, which induces high non-radiative carrier recombination ... » read more

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