Challenges And Outlook of Photonic-Integrated Circuit Packaging (Hanyang Univ.)


A new technical paper titled "Advanced Optical Integration Processes for Photonic-Integrated Circuit Packaging" was published by researchers at Hanyang University. Excerpt "This review discusses the latest developments in photonic integrated chip packaging at the component, chip, and system levels. It also highlights the current issues and challenges of these technologies and provides futur... » read more

Overview Of The End-to-End Autonomous Driving through V2X Challenge (Tsinghua, HK Univ., Stanford, TU Munich et al.)


A new technical paper titled "Research Challenges and Progress in the End-to-End V2X Cooperative Autonomous Driving Competition" was published by researchers at Tsinghua University, Hong Kong University, Stanford University, TU Munich, Imperial College of London et al. Abstract "With the rapid advancement of autonomous driving technology, vehicle-to-everything (V2X) communication has emerge... » read more

LLM Inference: Core Bottlenecks Imposed By Memory, Compute Capacity, Synchronization Overheads (NVIDIA)


A new technical paper titled "Efficient LLM Inference: Bandwidth, Compute, Synchronization, and Capacity are all you need" was published by NVIDIA. Abstract "This paper presents a limit study of transformer-based large language model (LLM) inference, focusing on the fundamental performance bottlenecks imposed by memory bandwidth, memory capacity, and synchronization overhead in distributed ... » read more

Statistical BER Analysis For Two Types Of Communication Systems In Chiplet Integration (TSMC)


An new technical paper titled "Fast and Accurate Jitter Modeling for Statistical BER Analysis for Chiplet Interconnect and Beyond" was published by researchers at TSMC. Abstract "In this paper, we investigate Statistical Bit Error Rate (BER) analysis for low-loss short-reach chiplet interface and high-loss long-reach serial interface. We used jitter filtering to account for the residue jitt... » read more

3D Heterogeneous Integration System To Accelerate LLMs (Georgia Tech)


A new technical paper titled "A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration" was published by researchers at Georgia Institute of Technology. Abstract "Conventional large language models (LLMs) are equipped with dozens of GB to TB of model parameters, making inference highly energy-intensive and costly as all the weights need to be ... » read more

Preventing End-to-End Slowdowns In Accelerated Chip Multi-Processors (Cornell University, Intel Labs)


A new technical paper titled "RACER: Avoiding End-to-End Slowdowns in Accelerated Chip Multi-Processors" was published by researchers at Cornell University and Intel Labs. Abstract "Recent chip multiprocessors incorporate several on-chip accelerators, marking the beginning of the Accelerated Chip Multi-Processor (XMP) era in datacenters. Despite the close proximity of accelerators and gener... » read more

Nanoimprint-Based Dielectric Patterning for Fine-Pitch Hybrid Bonding (Seoul National Univ. of Science and Technology)


A new technical paper titled "Hybrid Bonding with Polymeric Interlayer Dielectric Layers Patterned by Nanoimprint Lithography" was published by researchers at Seoul National University of Science and Technology. Abstract "Recent advancements in semiconductor technology have shifted the focus of innovation toward advanced packaging technologies featuring heterogeneous integration. Among thes... » read more

Implications of Scalable Neuromorphic Computing (Sandia National Laboratories)


A new technical paper titled "Neuromorphic Computing: A Theoretical Framework for Time, Space, and Energy Scaling" was published by researchers at Sandia National Laboratories. Abstract "Neuromorphic computing (NMC) is increasingly viewed as a low-power alternative to conventional von Neumann architectures such as central processing units (CPUs) and graphics processing units (GPUs), however... » read more

Intrusion Detection Approach for DoS Attacks on Automotive CAN bus (Dumarey Softronix, Politecnico di Torino)


A new technical paper titled "CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus" was published by researchers at Dumarey Softronix and Politecnico di Torino. Abstract "The Controller Area Network (CAN) protocol, essential for automotive embedded systems, lacks inherent security features, making it vulnerable to cyber threats, espe... » read more

On-Die And In-Package Interconnects: eBook


We live in the Information Age, but if information cannot get to where it's intended to go, it does no good. And the way information gets from here to there is through interconnects. This report focuses on different interconnect structures, such as lines, vias, buses, and networks-on-chip, and how they’re constructed. As always, we consider the design, test, reliability, and security impli... » read more

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