category: Top Stories

category: Auto, Security & Edge AI

Power Semi Wars Begin
By Mark LaPedus - 23 Oct, 2019 - Comments: 1

Several vendors are rolling out the next wave of power semiconductors based on gallium nitride (GaN) and silicon carbide (SiC), setting the stage for a showdown against traditional silicon-based devices in the market. Power semiconductors are specialized transistors that incorporate different and competitive technologies like GaN, SiC and silicon. Power semis operate as a switch in high-volt... » read more

Making Random Variation Less Random
By Ed Sperling - 21 Oct, 2019 - Comments: 0

The economics for random variation are changing, particularly at advanced nodes and in complex packaging schemes. Random variation always will exist in semiconductor manufacturing processes, but much of what is called random has a traceable root cause. The reason it is classified as random is that it is expensive to track down all of the various quirks in a complex manufacturing process or i... » read more

What’s The Best Advanced Packaging Option?
By Mark LaPedus - 17 Oct, 2019 - Comments: 2

As traditional chip designs become more unwieldy and expensive at each node, many IC vendors are exploring or pursuing alternative approaches using advanced packaging. The problem is there are too many advanced packaging options on the table already, and the list continues to grow. Moreover, each option has several tradeoffs and challenges, and all of them are still relatively expensive. ... » read more

Building An MRAM Array
By Katherine Derbyshire - 17 Oct, 2019 - Comments: 2

MRAM is gaining traction in a variety of designs as a middle-level type of memory, but there are reasons why it took so long to bring this memory to market. A typical magnetoresistive RAM architecture is based on CoFeB magnetic layers, with an MgO tunneling barrier. The reference layer should have zero net magnetization to make sure that it doesn’t influence the orientation of the free lay... » read more

Mask Making Issues With EUV
By Mark LaPedus - 17 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

Thomas Dolby’s Very Different View Of Progress
By Ann Mutschler - 16 Oct, 2019 - Comments: 4

Thomas Dolby’s hit songs “She Blinded Me with Science” and “Hyperactive!” catapulted him to international fame in the early '80s as a pioneer of New Wave and Electronica by combining a love for invention with a passion for music. The result defined an era of revolutionary music. As record company politics began to overshadow the joy of performing, Dolby turned his attention to Holl... » read more

Extending Portable Stimulus
By Brian Bailey - 16 Oct, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemens Business; Tom Anderson, technical marketing consultant for OneSpin... » read more

Pushing Memory Harder
By Brian Bailey - 14 Oct, 2019 - Comments: 4

In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

Focus Shifts To Wasted Power
By Brian Bailey - 10 Oct, 2019 - Comments: 0

Mobile phones made the industry aware of power, but now the focus is shifting to the total energy needed to perform a task. Activity that is unnecessary to perform the intended task is wasted power, and reducing it requires some new methodologies and structural changes within development teams. There is a broadening awareness about power. "The companies doing SoCs for mobile lead the charge ... » read more

Using Emulators For Power/Performance Tradeoffs
By Ann Mutschler - 10 Oct, 2019 - Comments: 1

Emulation is becoming the tool of choice for power and performance tradeoffs, scaling to almost unlimited capacity for complex chips used in data centers, AI/ML systems and smart phones. While emulation has long been viewed as an important but expensive asset for chipmakers trying to verify and debug chips, it is now viewed as an essential component for design optimization and analysis much ... » read more

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