category: Top Stories

category: Auto, Security & Edge AI

The Bumpy Road To 10nm FinFETs
By Mark LaPedus - 21 May, 2015 - Comments: 0

Foundry vendors are currently ramping up their 16nm/14nm [getkc id="185" kc_name="finFET"] processes in the market. Vendors are battling each other for business in the arena, although the migration from planar to finFETs is expected to be a slow and expensive process. Still, despite the challenges at 16nm/14nm, vendors are gearing up for the next battle in the foundry business—the 10nm nod... » read more

How Hard Is FD-SOI Design?
By Ann Mutschler - 21 May, 2015 - Comments: 0

Fully-depleted silicon-on-insulator ([getkc id="220" kc_name="FD-SOI"]) manufacturing technology reached of point of readiness for mass production at the end of March. Along with that, it’s now clear that while there are some impacts on the design flow, those impacts are not game changers. For one thing, the tools required are the same ones currently used for 28nm planar bulk CMOS. The onl... » read more

Waiting For Next-Gen Metrology
By Mark LaPedus - 21 May, 2015 - Comments: 0

Chipmakers continue to march down the various process nodes, but the industry will require new breakthroughs to extend IC scaling at 10nm and beyond. In fact, the industry will require innovations in at least two main areas—patterning and the [getkc id="36" comment="Interconnect"]. There are other areas of concern, but one technology is quickly rising near the top of the list—metrology.... » read more

One-On-One: Thomas Caulfield
By Mark LaPedus - 21 May, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about fabs, process technology and the equipment industry with Thomas Caulfield, senior vice president and general manager of Fab 8 at [getentity id="22819" comment="GlobalFoundries"]. Located in Saratoga County, N.Y., Fab 8 is GlobalFoundries’ most advanced 300mm wafer fab. What follows are excerpts of that discussion. SE: Last year, GlobalFoundr... » read more

IP Market Shifts Direction
By Ed Sperling - 20 May, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss intellectual property changes and challenges with Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and MSIP at [getentity id="22035" e_name="Synopsys"]; Kurt Shuler, vice president of marketing at [getentity i... » read more

Problems Ahead for EDA
By Brian Bailey - 19 May, 2015 - Comments: 0

Semiconductor Engineering sat down with [getperson id="11411" comment="Bill Neifert"], chief technology officer at [getentity id="22521" comment="Carbon Design Systems"]; [getperson id="11032" comment="Simon Davidmann”], chief executive officer for [getentity id="22036" e_name="Imperas”]; Randy Smith, vice president of marketing for [getentity id="22605" e_name="Sonics"] and Michel Courtoy,... » read more

Energy Harvesting Update
By Ed Sperling - 18 May, 2015 - Comments: 0

Manos Tentzeris, professor of electrical and computer engineering at the Georgia Institute of Technology, sat down with Semiconductor Engineering to discuss energy harvesting. What follows are excerpts of that conversation. SE: What is the state of energy harvesting and are we making progress. Tentzeris: The latest results are systems with efficiency up to 40% to 45% utilizing ambient UH... » read more

Power Management Verification Requires Holistic Approach
By Ann Mutschler - 18 May, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power management [getkc id="10" kc_name="Verification"] issues with Arvind Shanmugavel, senior director, applications engineering at [getentity id="22021" e_name="Ansys-Apache"]; Guillaume Boillet, technical marketing manager at [getentity id="22026" e_name="Atrenta"]; Adam Sherer, verification product management director at [getentity id="22032" e_... » read more

Rethinking Power
By Ed Sperling - 14 May, 2015 - Comments: 0

Power typically has been the last factor to be considered in the PPA equation, and it usually was somebody else's problem. Increasingly it's everyone's problem, and EDA companies are beginning to look at power differently than in the past. While the driving forces vary by market and by process node, the need to save energy at every node and in almost all designs is pervasive. In the server m... » read more

Trouble Ahead For IP industry?
By Brian Bailey - 14 May, 2015 - Comments: 0

[getkc id="106" kc_name="Power-aware design"] has risen from an afterthought to a primary design constraint for some design types. Initially it was smart phones and other battery operated devices. It has consistently expanded into additional areas including those plugged into the wall and those plugged into the grid. Some parts of the world are imposing restrictions on the power that a device c... » read more

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