category: Top Stories

category: Auto, Security & Edge AI

Ecosystem Changes
By Ed Sperling - 26 Mar, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss changes in the semiconductor ecosystem with Kelvin Low, senior director of foundry marketing at [getentity id="22865" e_name="Samsung Semiconductor"]; John Costello, vice president of product planning at [getentity id="22849" e_name="Altera"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"], and Michiel Ligthart, p... » read more

3 Key IoT Benchmarks
By Ed Sperling - 23 Mar, 2015 - Comments: 0

The [getkc id="76" comment="Internet of Things"] has been billed as the next huge opportunity for semiconductors—tens of billions of things connected to a centralized infrastructure, to people, and in many cases to each other. After conducting hundreds of interviews with executives, engineers and university professors from all facets of the global supply chain over the past year and reviewin... » read more

Searching For 3D Metrology
By Mark LaPedus - 19 Mar, 2015 - Comments: 3

In the previous decade, chipmakers made a bold but necessary decision to select the [getkc id="185" kc_name="finFET"] as the next transistor architecture for the IC industry. Over time, though, chipmakers discovered that the finFET would present some challenges in the fab. Deposition, etch and lithography were the obvious hurdles, but chipmakers also saw a big gap in metrology. In fact,... » read more

5 Reasons EUV Will Or Won’t Be Used
By Michael Watts - 19 Mar, 2015 - Comments: 1

Digging into this subject, there are five metrics that count in a lithography tool: resolution, throughput, defects, overlay, and reliability. So what does the best data tell us about the current state and realistic prognosis for [gettech id="31045" comment="EUV"]. Semiconductor Engineering posed this question to Matt Colburn, senior manager for patterning research at [getentity id="22306" comm... » read more

3D Effects At 20nm And Beyond
By Ann Mutschler - 19 Mar, 2015 - Comments: 0

At the 20nm process node and below, attenuated phase shift masks (PSM) are used in the photolithography process, which results in approximately 70nm of topography. This now must be accounted for using 3D mask approximation. Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], explained that in terms of [getkc id="80" comment="lithography"], where simulation-based technologies are used,... » read more

Challenges Mount For Patterning And Masks
By Mark LaPedus - 19 Mar, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Uday Mitra, vice president and chief technology officer for the Etch Business Unit at [getentity id="22817" e_name="Applied Materials"]; Pawitter Mangat, senior manager and deputy director for EUV lithography at [getentity id="22819" comment="GlobalFoundries"]; Aki Fujimura, chief executive at [getentity id="228... » read more

ATE: The Road Ahead
By Jeff Chappell - 19 Mar, 2015 - Comments: 0

Watching the ATE market is like having a front-row seat to watch the semiconductor industry's ups and downs, with none of the hype to confuse you. So 2014 was a very good market for SoC test, and it likewise a good year for SoCs. As we head into the latter half of this year and into 2016, however, a projected downturn in the mobile arena will likely put a crimp in those earnings. The prob... » read more

Issues And Options At 5nm
By Mark LaPedus - 19 Mar, 2015 - Comments: 0

While the foundries are ramping up their processes for the 16nm/14nm node, vendors are also busy developing technologies for 10nm and beyond. In fact, chipmakers are finalizing their 10nm process offerings, but they are still weighing the technology options for 7nm. And if that isn’t enough, IC makers are beginning to look at the options at 5nm and beyond. Today, chipmakers can see a p... » read more

First Time Success And Cost Control
By Brian Bailey - 13 Mar, 2015 - Comments: 0

First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

Thermal Is Still Simmering
By Ann Mutschler - 12 Mar, 2015 - Comments: 0

With the ever increasing sophistication in today’s high-performance [getkc id="81" kc_name="SoC"]s on top of sheer physics of device manufacturing, thermal is a much bigger concern than ever before. It is well understood that thermal and power are closely related, and there exists a vicious cycle between leakage power and temperature: leakage goes up, temperature goes up; temperature goes ... » read more

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