category: Top Stories

category: Auto, Security & Edge AI

Cadence Gobbles Up Jasper
By Brian Bailey - 21 Apr, 2014 - Comments: 4

2012 was the year that everyone remembers Synopsys going on an acquisition binge, but 2014 will go down as the year that Cadence Design Systems decided that EDA was worth investing in. Rather than placing investment bets outside of its core competence, Cadence bought Forte in February and now adds Jasper Design Automation to its fold. Jasper started life as Tempus Fugit in 1999 and became Ja... » read more

Executive Insight: CH Wu
By Ed Sperling - 21 Apr, 2014 - Comments: 0

Semiconductor Engineering sat down with CH Wu, president and CEO of Advantest Taiwan, to talk about business, politics, and his philosophy on what really motivates people. What follows are excerpts of that conversation. SE: Tell us a little about who you are and your background. Wu: I graduated from college with a degree in electrical engineering and started at Philips Electric, then moved ... » read more

Improving Yield Of 2.5D Designs
By Ann Mutschler - 18 Apr, 2014 - Comments: 0

While progress is being made on the packaging side of 2.5D design, more needs to be resolved when it comes to improving yields. Proponents of 2.5D present compelling benefits. Arif Rahman, a product architect at Altera, noted that the industry trend of silicon convergence is leading to multiple technologies being integrated into single-chip solutions. “2.5D/3D integration has multiple adva... » read more

What If EUV Fails?
By Mark LaPedus - 17 Apr, 2014 - Comments: 2

It’s the worst kept secret in the industry, but extreme ultraviolet (EUV) lithography will likely miss the 10nm node. So, chipmakers will likely extend and use today’s 193nm immersion lithography down to 10nm. This, of course, will require a complex and expensive multiple patterning scheme. Now, chipmakers are formulating their lithography strategies for 7nm and beyond. As it stands now,... » read more

Real Countries Have Fabs
By Ed Sperling - 17 Apr, 2014 - Comments: 3

Persistent rumblings about the sale of IBM’s semiconductor unit might have seemed absurd a couple decades ago—before IBM sold off its PC unit to Lenovo and lost the gaming chip business to AMD’s x86 chips—but no one is scoffing at the possibility these days. The reality is that IBM will never reach the volume necessary to be the No. 1 or No. 2 player in its segment. It’s not even i... » read more

Gaps In Metrology Could Impact Yield
By Mark LaPedus - 17 Apr, 2014 - Comments: 0

For some time, chipmakers have been developing new and complex chip architectures, such as 3D NAND, finFETs and stacked die. But manufacturing these types of chips is no simple task. It requires a robust fab flow to enable new IC designs with good yields. In fact, yield is becoming a more critical part of the flow. Yield is a broad term that means different things to different parts of the ... » read more

Billions And Billions Invested
By Mark LaPedus - 17 Apr, 2014 - Comments: 4

Over the years, next-generation [getkc id="80" kc_name="lithography"] (NGL) has suffered various setbacks and delays. But until recently, the industry basically shrugged its shoulders and expressed relatively little anxiety about the NGL delays. After all, optical lithography was doing the job in the fab and NGL would eventually materialize. Today, however, the mood is different. In fact, th... » read more

Time To Revisit 2.5D And 3D
By Mark LaPedus - 17 Apr, 2014 - Comments: 2

Chipmakers are reaching various and challenging inflection points. In logic, many IC makers face a daunting transition from planar transistors at 20nm to finFETs at 14nm. And on another front, the industry is nearing the memory bandwidth wall. So perhaps it’s time to look at new alternatives. In fact, chipmakers are taking a hard look, or re-examining, one alternative—stacked 2.5D/3D chi... » read more

A Guide To Advanced Process Design Kits
By Ernest Worthman - 14 Apr, 2014 - Comments: 1

The increasing complexity of design enablement has prompted manufacturers to optimize the design process. New tools and techniques, thanks to next-generation hardware and software, have provided a new platform for semiconductor and wafer design. Advanced PDKs are the solution and have been developed by foundries to optimize the design process and leverage and reuse intellectual property (IP) an... » read more

Architecting For Efficiency
By Ann Mutschler - 10 Apr, 2014 - Comments: 0

By definition, to be efficient is to perform or function in the best possible manner with the least waste of time and effort; having and using requisite knowledge, skill, and industry. As this relates to SoC design today, achieving the highest level of efficiency is a challenge with many dimensions. Efficiency comes in multiple ways. “One dimension would be power consumption,” said Oz Le... » read more

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