category: Top Stories

category: Auto, Security & Edge AI

More Rigor, Please
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor companies are embracing a single-platform strategy for their SoC designs, but sifting through the options can be quite a feat. While not wildly different from the traditional derivative approach, a single-platform strategy can mean different things to different companies. Sometimes it refers to a platform that is already successful in one application ... » read more

Experts At The Table: Debug
By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: What are the big issues with debug? ... » read more

More Test Needed For Integrated IP
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler As the use and reuse of design IPs and cores has reached approximately 70% of the content of an SoC, the need for both pre- and post-silicon test has increased. On the pre-silicon side, test comes in the form of verification IP. Driving the addition of more strenuous test approaches on this side is a combination of forces that impact design, noted Tom Hackett, prod... » read more

Applied To Buy TEL
By Mark LaPedus - 24 Sep, 2013 - Comments: 0

In a deal that could shake-up the fab tool landscape, Applied Materials has announced a definitive agreement to acquire rival Tokyo Electron Ltd. (TEL) in a stock deal valued at around $9.3 billion. Under the terms of the blockbuster deal, Applied Materials will own approximately 68% of the new company and TEL will own about 32%.  The combined entities will have a new name, dual headquarter... » read more

Litho Roadmap Remains Cloudy
By Mark LaPedus - 19 Sep, 2013 - Comments: 0

By Mark LaPedus For some time, the lithography roadmap has been cloudy. Optical lithography has extended much further than expected. And delays with the various next-generation lithography (NGL) technologies have forced the industry to re-write the roadmap on multiple occasions. Today, there is more uncertainty than ever in lithography. Until recently, for example, leading-edge logic chipma... » read more

What’s After 3D NAND?
By Mark LaPedus - 19 Sep, 2013 - Comments: 0

By Mark LaPedus Planar NAND flash memory is on its last scaling legs, with 3D NAND set to become the successor to the ubiquitous 2D technology. Samsung Electronics, for one, already has begun shipping the industry’s first 3D NAND device, a 24-level, 128-gigabit chip. In addition, Micron and SK Hynix shortly will ship their respective 3D NAND devices. But the Toshiba-SanDisk duo are the lo... » read more

MRAM Begins To Attract Attention
By Mark LaPedus - 19 Sep, 2013 - Comments: 0

By Mark LaPedus In the 1980s, there were two separate innovations that changed the landscape in a pair of related fields—nonvolatile memory and storage. In one effort, Toshiba invented the flash memory, thereby leading to NAND and NOR devices. On another front, physicists discovered the giant magnetoresistance (GMR) effect, a technology that forms the basis of hard disk drives, magnetores... » read more

Executive Briefing: Soitec CEO
By Mark LaPedus - 19 Sep, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss FD-SOI, solar and various technology trends with André-Jacques Auberton-Hervé, chairman and chief executive of Soitec, a supplier of silicon-on-insulator (SOI) substrates, solar concentrators and other products. SMD: The digital process roadmap is moving in several directions. Some pure-play foundries will offer ... » read more

Mask Data Prep Issues Compounding At 20nm
By Ann Mutschler - 19 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to mask data prep—the step in the design and manufacturing flow that occurs just after optical proximity correction (OPC)—challenges have continued to rise with the subsequent moves to smaller geometries. This is driven by the scaling demands of delivering about a 50% area shrink from node to node on a two-year cycle, and thus dictates the lithog... » read more

Front End Comes To The Back End
By Jeff Chappell - 19 Sep, 2013 - Comments: 0

By Jeff Chappell For outsourced assembly and test (OSAT) houses either planning for or already offering through-silicon via (TSV) capability for their 3D packaging efforts, this has meant the front end is coming to the back end, in a manner of speaking. A bit of an exaggeration perhaps, as most generalizations are. But thanks to TSVs, in a very real sense some of what would typically be the... » read more

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