Mind The Gap


By Ed Sperling Throughout system-level design there are gaps. High-level modeling doesn’t connect directly to RTL code. Synthesis and high-level synthesis remain worlds apart. There are even gaps in the expertise, from the people who handcraft RTL to those who take it for granted. Some of these gaps will get closed over time. Others will never be closed. In same cases it doesn’t matter.... » read more

Your Light Bulb Is Calling


By Pallab Chatterjee The mobility that is best associated with “smart phone” functionality is making its way into most other electronic systems. At ISSCC and even the Strategies in Light conference, systems and products were being shown featuring standard RF interfaces. The RF is being made available as standalone die for multi-die and 3D packaging, as well as in SoC IP blocks. The func... » read more

Make vs. Buy


By Ann Steffora Mutschler The age-old question of whether to make or buy is time immemorial, and is particularly true for the cyclical semiconductor industry. At the end of the day, the answer comes down to how the decision maker feels about having or losing control. Fifteen years ago, whether to make or buy something—be it the design, libraries, memory, implementation, verification, te... » read more

Smart-Grid Designs Solve Low-Power Riddles


By Ellen Konieczny Imagine that you go to your kitchen to get a drink and pass your home’s energy-usage monitor. Due to a recent heat wave, you see that your energy usage is already at what it usually is for the entire month. Yet you’ve still got one week left in your billing cycle. To keep the bill low, you turn your A/C thermostat up a degree and make a mental note to not keep lights o... » read more

Partitioning For Power


By Pallab Chatterjee Design partitioning for power in an IC is driven by which functions are on simultaneously. The new generation of “smart” power management chips introduces new constraints to the task. Case in point: The new LP8725 from National Semiconductor. These chips have multiple DC-DC converters and both analog and digital low-dropout regulators (LDOs), with a common I2C inter... » read more

The Growing Problem With Parasitic Extraction


By Ed Sperling Like everything else in semiconductor engineering at advanced process geometries, parasitic extraction is getting much more difficult at each node. There’s more circuit data to analyze, less distance between wires and much more to sort through. In addition, a 10% error in accuracy at 90nm might have been tolerable, while at 28nm it can completely change how a chip works. ... » read more

Rethinking Test


By Ann Steffora Mutschler The responsibility of semiconductor test has long sat solely with the test engineer as the chip designer focused on the functionality of the device. However, particularly in low-power designs, when the device is being tested, much higher power levels are applied than normal functional operation – sometimes causing the device to fail. This ‘false failure’ c... » read more

Low-Power And RF Design Heighten Signal-Integrity Concerns


By Ellen Konieczny As active devices and interconnect wires shrink and are placed closer together with the march of Moore’s Law, signal integrity is becoming a huge concern. If it is not maintained, a design’s future may be marred by lower yields, unreliable performance, and failure to work efficiently—if at all. For low-power and radio-frequency (RF) designs, which are being prod... » read more

Listening In With Better Audio


By Pallab Chatterjee The high profile discussion on new consumer products has been high definition-video and high-definition TV broadcast. The other end of the experience is starting to catch up with improved audio. Since the shift from LPs and CDs has taken place towards downloadable portable audio data, there have been complaints from the listeners about the quality of the sound. The f... » read more

Should Sign-Off And Implementation Be Separate Tools?


By Ann Steffora Mutschler In the last stages of design, how data is readied for manufacturing used to be relatively straightforward. Point tools were used to implement the design via a place and route tool then the design was “signed off” with physical verification software. Sign-off is the gate the design goes through before it can go into manufacturing. The design must meet the qua... » read more

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