GaN Power Devices Power Up

Key Takeaways:

• GaN devices are gaining traction due to their ability to tolerate higher voltages.
• New approaches such as chiplets offer faster switching with less loss.
• The first applications to benefit from GaN will be low-voltage consumer devices; industrial applications require more work.

As electrical power displaces fossil fuels in more applications, system designers need switches and power converters that can handle both higher source voltages and more demanding short circuit and overvoltage spikes.

Wide-gap semiconductors, such as gallium nitride (GaN), are particularly interesting to device designers because their higher breakdown strength and higher thermal conductivity support high-power-density applications. Still, their ability to tolerate common failure conditions is relatively untested.

The fundamental building block for GaN power devices, the high electron mobility transistor (HEMT), depends on a GaN/AlGaN heterostructure. Lattice strain at the interface between the two materials causes a discontinuity in the energy band structure. As a result, a two-dimensional electron gas (2DEG) forms. Carriers have very high mobility within this layer — above 1,500 cm²/V-sec — but very low mobility outside of it. In this absence of an external bias, the 2DEG forms a conductive path.

Thus, HEMTs in their most basic form are normally-on, depletion-mode devices. Normally-off, enhancement-mode operation is preferable in silicon logic to reduce power consumption. In power devices, it’s essential for safe operation. Several different designs have demonstrated enhancement-mode operation. One of the most successful uses a magnesium-doped p-GaN gate. It raises the surface potential of the barrier layer, depleting the 2DEG in the gate region even at zero bias.[^⁠1]

Because the GaN/AlGaN heterostructure depends on lattice strain to confine the 2DEG, careful strain engineering is essential for successful fabrication of GaN power devices. To achieve high-quality superlattices on silicon without cracking or dislocations, manufacturers typically use a graded AlGaN buffer layer, followed by deposition of the device structure. This requirement, in turn, means that most GaN power devices use lateral structures and horizontal channels. The vertical channels that are often seen in silicon and SiC power devices are more difficult to achieve in GaN.

If device-quality GaN is difficult to fabricate on its own, it is even more difficult to integrate with other materials. Yet, as Han Wui Then and colleagues at Intel Foundry explained, that’s exactly what many applications require. The Intel Foundry group demonstrated a GaN-on-silicon-based chiplet platform for low-voltage, high-density power electronics.

By reducing the distance between circuit elements, chiplets offer lower resistive losses and faster switching. On the other hand, to minimize resistive losses and maximize heat dissipation, chiplets should be much less than 50 microns thick. Moreover, silicon circuit elements need to reside on the same die as GaN elements. There’s no room for a separate CMOS companion die for controller circuits and similar components.

To resolve the tradeoff between GaN quality and silicon quality, this research transferred a silicon PMOS layer onto GaN N-MOS HEMTs, with a unified process design kit. They demonstrated a full library of on-die circuits, including multiplexers, inverters, and ring oscillators.^⁠[2] According to Intel, these devices are, at 19 microns thick, the world’s thinnest GaN chiplets.

Fig. 1: TEM micrograph showing GaN N-MOS HEMT monolithically integrated with silicon PMOS. (Ref. 2)

Isolation and integration
While increasing device density reduces resistive losses, it makes isolation between devices harder. It’s especially difficult to prevent crosstalk when devices share a common source terminal or are back-gated through a common substrate.

For instance, a half-bridge circuit, a fundamental power electronics element, has a high-side switch and a low-side switch with different source terminals. When the high-side switch is on, the node connects to the positive power supply line. When the low-side switch is on, the node connects to ground. SOI and other engineered substrates can provide separate “islands” for each transistor, but add cost and design complexity. Similarly, bi-directional switches are frequently used in various kinds of power converters. When the two source terminals share a substrate, crosstalk can degrade device resistance. Again, active substrate control circuits add cost and design complexity.

Zheng Wu and colleagues at the Hong Kong University of Science and Technology sought to resolve this issue by building two 2DEG channels in the same heterostructure. Their structure uses two AlN/GaN pairs (figure 2), with an AlGaN layer on top and a p-GaN gate on top. The AlN layer in the middle of the stack creates a hole-spreading channel that blocks vertical hole transport. Holes injected from the p-GaN gate are swept to this layer and recombined out of existence, suppressing crosstalk.[^⁠3]

Fig. 2: Cross-sectional view and schematic band diagram of dual-channel power integration platform. (Ref. 3)

While crosstalk is a serious issue, power devices for industrial applications also need to be able to tolerate short-circuit and overvoltage conditions. A group at the University of Hong Kong suggested that back-gating effects might improve short circuit resilience by mitigating current crowding along the channel. Their bi-directional switch devices were able to withstand repetitive 30 microsecond short-circuits, far beyond the 10 microseconds required by typical designs. Their devices shared a common substrate. In contrast, hybrid devices with separate substrates had much lower short-circuit resilience.[^⁠4]

Reliability and interface quality
The GaN/AlN interface is critical to other aspects of GaN device performance, as well. When these layers are deposited by MOVPE (metal-organic vapor phase epitaxy), unintentional carbon incorporation into the GaN layer can lead to an AlGaN gradient between the two materials.

T. Lee and colleagues at Asahi Kasei Corp. suppressed carbon incorporation by using triethylgallium instead of trimethylgallium as the gallium precursor, and in the process they nearly doubled the 2DEG density and reduced sheet resistance by nearly 4X. Etching a recess in the AlN barrier layer further improved the device by reducing contact resistance.[^⁠5]

High field conditions, such as short-circuits and overvoltage events, accelerate channel electrons. These “hot” electrons stress the device’s access region, in particular. According to Haohao Chen of Southern University of Science and Technology (Shenzen, China), magnesium, when used as a p-GaN dopant, can diffuse into the AlGaN barrier layer where it behaves as a deep trap. Chen’s group used selective epitaxy with a silicon dioxide masking layer to deposit p-GaN in the desired areas without damaging the underlying AlGaN layer. Their device demonstrated a breakdown voltage of 495 V, as opposed to 321 V for conventional HEMT devices. Devices using selective epitaxy also showed improved stress reliability and short circuit robustness.[^⁠6]

With overvoltage conditions, GaN HEMTs suffer destructive breakdown failures. Vertical silicon and SiC devices are able to tolerate overvoltage spikes through a non-destructive avalanche breakdown. Lateral GaN HEMTs tend to undergo destructive breakdown instead. Without a PN junction, Jingjing Yu and colleagues suggest the devices may be unable to remove carriers generated by impact ionization effectively. As an alternative solution, they used a thinned p-GaN layer to define a punch-through gate. (Figure 3) In the off state, a depletion region begins at the drain side and expands toward the source side. Once the layer is fully depleted, current can punch through to the 2DEG layer, allowing non-destructive failure.[^⁠7]

Fig. 3: Proposed punch-through HEMT design, with cross-sections. (Ref. 7)  

Conclusion
GaN-based power devices are now the technology of choice for low-voltage applications like chargers for consumer electronics. Industrial applications, in contrast, present much more demanding stress environments, requiring resilience against short circuits and high-voltage transients. Solutions are emerging in the form of innovative device designs and process optimization, but much work remains.

References

1. Yaozong Zhong, et al., “A review on the GaN-on-Si power electronic devices,” Fundamental Research, Volume 2, Issue 3, 2022, Pages 462-475, https://doi.org/10.1016/j.fmre.2021.11.028
2. H. W. Then et al., “GaN Chiplet Technology Based on 300mm GaN-on-Silicon,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353652.
3. Z. Wu et al., “A Crosstalk-Free GaN-on-Si Power Integration Platform for Integrated Half-Bridge Circuits and Bi-directional Switches,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353705.
4. H. Cui et al., “Intrinsically Exceptional Short-Circuit Robustness (tSC > 30 µs, ISC > 230 A) in Monolithic Bidirectional GaN-on-Si Power HEMTs,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353782.
5. T. Lee et al., “Low-Resistance and Current-Collapse-Free MOVPE-Grown Pseudomorphic AlN/GaN/AlN HEMTs on AlN substrates,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353579.
6. H. Chen et al., “Hot-Electron Hardening in GaN-based Power Devices by Selective p-GaN Gate Epitaxy,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353527.
7. J. Yu et al., “E-Mode p-GaN Gate Punch-Through HEMT with Robust Non-Destructive Drain Breakdown,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353769.