Inside Process Technology

Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. What follows are excerpts of that conversation.

SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around the corner. What do you see happening at these advanced nodes, particularly at 7nm?

Fried: Most people are predicting evolutionary scaling from 14nm to 10nm to 7nm. It’s doubtful that we will see anything really earth-shattering in these technologies. And so, a lot of the challenges come down to patterning. We are going to see multi-patterning schemes really take hold at more levels. For example, the fins are now based on self-aligned double patterning. People will move into self-aligned quad patterning. The gates are maybe self-aligned double. Now, they will move into self-aligned quad. So, that’s going to be a big expense, because each level is going to have multiple passes and multiple cuts.

SE: What are the challenges here?

Fried: One of the big challenges is the multi-patterning piece. The second piece is that as you go through these evolutionary scaling points, there are a lot of other things that could break. We are trying to deposit very thin films in very high aspect ratio trenches. Again, with finer patterning, we will need incredibly low tolerances for etch. Atomic-level variability for both etch and deposition is going to get pressed to the limits in these technologies.

SE: What else?

Fried: There’s a crossover technology coming up here. What I mean by crossover is when is EUV? The challenge is that you will have to pick a technology and commit that technology to use EUV. This is long before you can really use it in the fab for development. That’s a tremendous challenge. 7nm might be a technology that the foundries are going to commit for EUV. But they will spend the next two or three years developing the technology without high-volume EUV tools.

SE: Why is that an issue?

Fried: Basically, you will need to have all of these multi-patterning schemes developed for the development wafers. Then, you must vet out a technology that may not even use them. You will have to figure out design rules and process validation ground rules on a technology that will be developed without the lithography manufacturing platform. There is a crossover out there somewhere. Maybe it’s 7nm. But essentially, you are putting a technology together on a lithography platform that doesn’t exist yet. That’s a big challenge here.

SE: What does that mean for foundries and their customers?

Fried: If you think about that challenge, you have to also think what that means economically. That, I believe, is why people are pushing customers towards 7nm rather than 10nm. The strategy is to develop the technology and the hard process aspects for 10nm. And then they take that, shrink it a little bit, and perhaps get EUV in at 7nm. The only thing they are figuring out at 7nm is the EUV piece. All of the other challenging processes are figured out at 10nm. What that also means is if it works, 7nm will be much cheaper to produce than 10nm.

SE: Still, foundry customers must make some tough choices. For example, do they go from 16nm/14nm to 10nm? Or do they skip 10nm and jump to 7nm?

Fried: It’s a time, cost and risk balance. Each customer will have to balance their cost and timeline risk very carefully to make that choice. Basically, 10nm is a significantly lower risk. It will happen on a relatively predictable time line. But it will have the understood density penalty of 10nm with a pervasive deployment of multi-patterning. And it will have the cost penalty, as far as we can tell, of not using EUV. 7nm starts to look like a real technology scaling node. It will start to drive cost down. If my predictions are right, they may try and squeeze 7nm into the high-volume manufacturing path of EUV.

SE: TSMC and others might wait and insert EUV at 5nm, right?

Fried: Clearly, TSMC is working on EUV. They don’t plan to deploy it for 7nm in high-volume. It may be deployed at 5nm. That may be one generation off in the crossover point. But the generation where they finally get EUV in, it starts to look like a real scaling node.

SE: What about new technologies like nanowire FETs and III-V materials in the channels?

Fried: I am looking for these earth-shattering breakthroughs. When do we get nanowires? When do you get alternative channel materials? I don’t see things happening fast enough on those groundbreaking options for it to happen at 7nm. I don’t foresee earth-shattering transistor elements in the next generation or two.

SE: Any thoughts on the cadence of the nodes?

Fried: Everybody, including Intel, is saying the technology nodes are stretching out. One day, these nodes might be three years apart instead of two. Maybe longer as we go further out.

SE: Let’s focus on . Where is that heading?

Fried: If you look around, there’s multi-patterning, EUV and DSA. A couple of years ago, EUV was supposedly coming. The patterning and integration community said that all we had to do was glue together this multi-patterning thing a little bit, because then EUV would save us. EUV has been pushed out long enough that multi-patterning has really grown some muscle. What I see is a lot more rigor, discipline and intensity on the multi-patterning front. The industry really understands the problems and is driving it to high-volume manufacturing by necessity. It has gone from a garage band to something professional over the last couple of years.

SE: If EUV misses the 5nm window, the industry is talking about self-aligned octuple patterning (SAOP). Some say SAOP is impossible. Any comments?

Fried: Two years ago, we said the same thing about SAQP. Then, we graduated from SADP to SAQP. What about SAOP? Today, it’s seems out of the question. But we are one multiplication away from SAOP.

SE: What about EUV?

Fried: EUV is making huge progress. For example, you have the pellicle, resist defectivity and other issues. Those things were dark clouds a few years ago. Now, the problems are clearly defined and there are competing solutions. People are working on them and those will be solved.

SE: What about DSA?

Fried: We are going to start to see more DSA, but not necessarily for conventional patterning. The first time we see DSA will be in pattern healing or pattern repair. Again, that will be an incremental improvement. It will be an evolutionary addition to the patterning scheme. It will not be a groundbreaking or earth-shattering change, especially in logic. We may see DSA for memory, because the designs are so much more regular. But we are still pretty far away from high-volume manufacturing applications for DSA.

SE: Which lithographic technologies will be the ultimate winners and losers?

Fried: Everyone wants to know which technology is going to win—multi-patterning, EUV or DSA. It’s been my view that all three of them are going to win. They may all live in the same technology and flow in the foundry.

SE: Can you give us an example?

Fried: By the time we get EUV inserted, for example, it might require EUV with SADP. It might also require SADP with DSA healing. It might be DSA in one layer and EUV in another layer.

SE: The winning lithographic technology comes down to cost, right?

Fried: Everything gets back to cost. One way to look at cost is through patterning fidelity. Then, there is process cost. This involves time and throughput.

SE: Besides patterning, the back-end-of-the-line () is another major challenge, right?

Fried: The back-of-the-line is becoming limited. Nobody is scaling the low-k dielectric. Nobody has come up with another metallization scheme to replace copper. I don’t see groundbreaking changes in the backend. These are problems. In effect, we are squeezing the same technology for multiple generations.

SE: Another issue is low-k dielectrics, right?

Fried: Nobody has moved past a k-effective beyond about 2.4. People have played around with 2.2. But the reliability is really tricky down there. People are also working on new liners and things like that, but it’s really challenging to get the RC delay down in the backend. In fact, the RC delay is going up exponentially. That’s limiting overall product scaling significantly. Again, unless someone comes up with an alternative metallization scheme, or an alternative pitch layer, we’re in trouble in the backend as well.

SE: Let’s switch gears. How do you see the 3D NAND market going?

Fried: 3D NAND is an amazing innovation. By moving the bit-string into the third dimension, this technology eases many of the patterning-scaling challenges, at least for a generation or so.

SE: What are the challenges with 3D NAND?

Fried: It has introduced several fairly complex and new processes, such as a deep etch through a multi-layer stack. This etch is really complex. Uniformity is absolutely critical to the performance of the memory device. Billions of these holes are being etched on each die and across the entire 300mm wafer.

SE: What else?

Fried: Once the etch is complete, the amount of processing that takes place inside that hole is also pretty impressive. It rivals or even maybe exceeds the complexity of the DRAM stacked capacitor formation process. Again, uniformity of these processes is critical. So, from my perspective, much of the challenge here is focused on variability control of several key processes. This is either control from the process/equipment side, or integration techniques that make the flow robust/insensitive to variation.

SE: Any thoughts on next-generation memories like MRAM, phase change or ReRAM?

Fried: I would expect these advanced memories to first find homes in applications that recognize or leverage one of their unique advantages. This is long before we ever settle on one winner. I would also expect there to be several different technologies that win in the end, just as SRAM, DRAM and NAND have coexisted for generations.

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