A new technical paper “High-κ dielectric van der Waals integration on 2D semiconductors for three-dimensional complementary logic systems” was published by researchers at Sungkyunkwan University and KAIST.
“This scalable methodology enables the vertical integration of complementary logic, demonstrated by complementary FET inverters and ring oscillators, establishing a promising route toward three-dimensional, energy-efficient logic technologies,” states the paper.
Find the technical paper here. November 2025. Preprint.
Kang, T., Park, J., Lee, S.Y. et al. High-κ dielectric van der Waals integration on 2D semiconductors for three-dimensional complementary logic systems. Nat Commun (2025). https://doi.org/10.1038/s41467-025-66770-0. Creative Commons license.
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