Precision Patterning Options Emerge For Advanced Packaging

The chip industry is ratcheting up investments in advanced packaging as it strives to keep pace with demands for increased functionality and higher performance, including novel patterning technologies that can reduce costs and speed time to market.

Success in advanced packages is partly dependent on effectively managing the interconnectivity between the chips, which requires increasingly precise photolithography patterning of substrates. These substrates need to align perfectly with chiplets and their interconnects in order to achieve the necessary performance, and they need to be engineered to withstand mechanical stress that can cause cracks and warpage during assembly.

“Patterning for advanced packaging is a big problem because we’re getting to lower and lower line spacing,” says Calvin Cheung, vice president of engineering at ASE. “A typical package substrate might have RDL lines/spaces of 25/25µm, but advanced node chips might have requirements down to 2/2µm. Making those connections requires advanced techniques like laser-direct imaging (LDI) to ensure precision and alignment.”

In addition to finer RDLs, integrating multiple chips requires the creation of complex structures on the substrate, such as through-silicon vias (TSVs) and micro-bumps. Those are essential for achieving high-density integration and enhanced performance, but they also present significant technical challenges that demand precise patterning techniques.

The process for patterning TSVs involves several steps, including deep reactive ion etching (DRIE) to create the via holes, dielectric deposition, barrier metal, and via filling with a conductive material, which typically is copper. Each step must be meticulously controlled to prevent misalignment and ensure the vias maintain their intended electrical properties.

“TSVs offer the best option for an interconnect solution with the lowest parasitics,” says Brian Hwang, vice president and fellow at Amkor Korea. “However, the challenge lies in the precise patterning and alignment, which is critical to maintain signal integrity and reduce resistance.”

Micro-bumps serve as tiny connectors between stacked dies, facilitating the transfer of electrical signals and power. These bumps are significantly smaller than traditional solder bumps. They typically range in size from 10/10µm down to 2/2µm. This reduction in size allows for higher interconnect density and reduced pitch, which is crucial for the high-density integration. But patterning micro-bumps is a challenge. It requires uniform sizes and shapes, precise placement, and the integrity of the bumps needs to be maintained during subsequent processing steps. Misaligned or defective micro-bumps can lead to signal degradation, increased resistance, and even complete failure of the device.

There is also a need to manage the mechanical stress that arises during the fabrication and operation of these devices. The differences in thermal expansion coefficients (CTE) between materials used in the package causes warpage, potentially leading to cracks or delamination. This is particularly problematic for TSVs, which are subjected to considerable mechanical stress due to their vertical structures and the thermal cycling they experience during operation.

“When you put multiple chips on a package, you’re going to have mechanical stress,” says ASE’s Cheung. “That stress creates warpage on the package. We try to look at different materials and different package software to address all those issues.”

At least part of that can be addressed through better modeling of power inside a package. “While some people say Moore’s Law is beginning to slow down, there are still devices out there with a billion transistors on a chip,” said William Ruby, director of product management for Synopsys’ power analysis products. “Power density is huge. That leads our customers to say, ‘We need to look at it very holistically — all the way from software to architecture. Power affects thermal, it affects reliability, and it affects the cost of packaging and cooling.”

Channeling that power to the transistors more effectively can reduce some of the heat, which causes warpage. And moving signals back and forth over shorter distances and through wider high-density interconnects (HDIs) can further reduce the thermal effects. But HDIs add yet another challenge for patterning in advanced packaging. Creating HDIs involves patterning multiple layers of circuitry with fine lines and micro-vias, providing the necessary pathways for electrical signals in compact packages. Precision and alignment in patterning is crucial to ensuring signal integrity and performance in high-speed and high-frequency applications.

“Patterning on advanced packaging substrates, especially for different nodes with different interconnectivity needs can lead to mechanical issues and warpage,” adds Cheung. “The chip-package interface requirements vary across these nodes, necessitating a careful balance to manage stress on the package. Designing the package to distribute this stress effectively requires close cooperation between the design and packaging teams.”

i-line lithography
I-line steppers, utilizing a 365nm wavelength light source, are the mainstay lithography tools for advanced packaging. They offer high resolution down to 1.0µm and overlay accuracies below 200nm.

The most common field size is 52mm x 68mm, frequently used for its ability to provide a large exposure area on panels in a single pass. This minimizes stitching and is particularly beneficial for applications like fan-out wafer-level packaging (FOWLP) and panel-level packaging (PLP), which require large, detailed patterns. Another common field size, 55mm x 55mm, is often used in processes where consistent patterning is required over a relatively large area. Advanced vacuum chuck designs and panel-feeding systems help manage substrate warpage, ensuring effective processing even for substrates with significant deformation.

“When considering substrates, it’s crucial they aren’t heavily distorted,” says Doug Shelton, marketing manager at Canon. “For large advanced packages, it’s more about the interposers. You’re going to be stacking and interconnecting chips somehow, creating grids or patterns on the substrate with components assembled onto them. In contrast, with typical fan-out wafer-level packaging, you assemble first and then add the wiring, which is more challenging because the die can shift.”

However, i-line steppers face limitations with the most advanced nodes requiring resolutions below 1.0µm. Deep UV (248nm) lithography is being considered, but it’s an expensive option in the packaging arena. Other techniques, like multi-beam maskless lithography (MBML), are being explored as more cost-effective alternatives for extremely fine patterning. Additionally, while large field sizes minimize stitching needs, it remains an issue for extremely large panels, potentially introducing alignment errors. Managing these errors adds complexity and cost to the packaging process.

Scaling up to panel-level processing also requires adapting or redesigning existing lithography tools. This includes modifications to optics, stage movement, and control systems to maintain the necessary precision and throughput. Although this scaling increases complexity and cost, it offers significant advantages in integration density and performance. Advanced techniques such as or step-and-scan systems (scanners) are required to manage the larger substrate areas, which adds to the overall manufacturing cost. Scaling also creates challenges in mask alignment and exposure. Mask misalignment across the panel can result in defects. Additionally, ensuring uniform exposure across a larger substrate is difficult and can lead to inconsistent patterning.

New materials
To address some of these patterning challenges, the industry is exploring a variety of alternative materials that offer better thermal and mechanical properties and hold up better under the stress of differing requirements for the package substrate. One such material is liquid crystal polymer (LCP), which exhibits low CTE and excellent mechanical flexibility. LCPs are used to create substrates that can withstand the thermal and mechanical stresses encountered during the fabrication and operation of multi-chip packages.

Another promising material is polyimide, known for its high thermal stability and mechanical strength. Polyimide films are often used as stress buffers in semiconductor packages, effectively absorbing the mechanical stress caused by thermal cycling. This reduces the likelihood of warpage and enhances the overall reliability of the device. Additionally, polyimides are used as dielectric layers in advanced packaging, providing electrical insulation for the fine-pitch interconnects while maintaining mechanical integrity.

Glass substrates are a newer potential solution being explored for advanced packaging. Glass has a low CTE, which closely matches that of silicon, making it an excellent material for reducing thermal stress. The use of glass interposers in 2.5D and 3D packaging provides a stable platform that minimizes warpage and mechanical failures. Glass also offers superior electrical insulation properties, which are essential for maintaining signal integrity in high-density interconnects.

“Glass has a lot of nice characteristics,” says Dick Otte, CEO of Promex Industries. “You can get good CTEs. It’s also biologically compatible with many things. The metallization systems now are coming along for TSVs. And there are companies like Mosaic Microsystems building things on glass that are very thin — 100 microns — as a standard substrate. It’s still not in the mainstream, but it’s coming.”

In addition to these materials, the industry is investigating advanced composites and hybrid materials that combine the benefits of different substances. For example, copper-polyimide laminates offer the electrical conductivity of copper with the mechanical flexibility of polyimide.

PLP and FOWLP
Panel-level packaging (PLP) and fan-out wafer-level packaging (FOWLP) benefit significantly from new materials and innovative patterning techniques. PLP, in particular, involves larger substrate sizes compared to traditional wafer-level processes.

FOWLP offers enhanced electrical performance and thermal management by redistributing the I/O pads across a larger area. However, FOWLP also faces challenges in lithography due to the need for fine line and space patterning on non-silicon substrates. Achieving high-resolution patterns on these substrates necessitates the use of advanced lithography techniques such as laser direct imaging (LDI).

“Advanced packaging helps solve a lot of problems at the system level instead of trying to integrate everything into a monolithic chip,” says Harry Levinson, principal lithographer at HJL Lithography. “For example, while logic circuits shrink nicely, memory and I/O devices often don’t scale as well. By reassembling designs at the package level, we can make lithography processes more cost-effective, avoiding the need to use expensive techniques where simpler methods suffice.”

Creative solutions
Addressing the numerous challenges in patterning for advanced packaging has led to innovative solutions that push the boundaries of traditional lithography. Emerging technologies like programmable masks, direct write, and multi-beam e-beam lithography are proving to be viable alternatives to conventional methods, offering increased flexibility, precision, and efficiency.
A Canadian start-up, for example, has developed programmable mask technology to reduce the high costs and long lead times of producing individual masks for patterning in advanced packaging. Targeted for high-mix, low-volume production environments, this mask features a 500nm pitch limit.

“These pixels are controlled using MEMS technology — specifically a variable Fabry-Perot interferometer, which adjusts the light transmission by changing the height between two layers,” explains Richard Beaudry, CEO of Digitho Technologies. “The mask can adjust dynamically for each exposure, making it possible to create unique patterns and 2D codes for chip identification and serialization.”

Fig. 1: Programmable mask prototype. Source: Digitho Technologies

Other technologies forgo the mask altogether. LDI enables precise patterning on non-silicon substrates by directly writing the desired pattern onto the photoresist-coated surface using a focused laser. LDI provides high resolution and flexibility, allowing for the creation of the complex patterns required in FOWLP. However, LDI is still an exposure process that needs to be optimized to handle larger substrate sizes and ensure uniform exposure across the entire panel.

An alternative method for creating high-resolution patterns without the need for masks is maskless exposure lithography. This system uses focused beams to directly pattern the substrate, offering significant advantages in flexibility and resolution. Direct write systems are particularly valuable for applications that require frequent design changes or high customization levels, despite the slower throughput compared to traditional photolithography.

One way to address the slow throughput of direct write patterning is to bundle multiple miniature electron beams operating in parallel that are capable of exposing a wide-field in a single pass. Multicolumn e-beam lithography (MEBL) offers some advantages over traditional direct-write and i-line lithography methods in terms of speed and flexibility. While creating optical masks can take weeks, MEBL can write designs in hours, thereby reducing costs and accelerating the time to market.

“Multibeam lithography offers a complementary solution for patterning in advanced packaging,” says David Lam, CEO of Multibeam. “It is particularly valuable in rapid prototyping and high-mix production environments where speed and flexibility are required.”

The ability to directly write intricate patterns without the need for masks not only saves time but also offers greater design latitude. This is crucial in advanced packaging, where high-density interconnects and complex patterns are required. By eliminating the mask creation process, the MEBL system reduces lead times and operational costs, enabling faster adaptation to design changes. This makes it an ideal solution for applications such as FOWLP or PLP, where precision and flexibility are paramount. The system’s high throughput and precision significantly enhance the efficiency of advanced packaging processes, facilitating quicker iterations and innovations in semiconductor manufacturing.

Combining these technologies presents a promising avenue for future advancements. For instance, integrating programmable masks with direct write capabilities could enhance throughput while maintaining the required precision.

“These new technologies could be highly beneficial for packaging,” says Levinson. “Direct write is ideal for packaging for multiple reasons, but current systems are slow. Combining programmable masks with direct write capabilities could improve throughput and provide the needed precision. A hybrid approach could be very effective for advanced packaging applications.”

Together, these advancements in lithography technologies represent a concerted effort to overcome existing limitations in patterning for advanced packaging, ensuring that the industry can continue to innovate and meet the demands of next-generation semiconductor devices. The advancement and proliferation of high-density interconnect technologies in semiconductor packaging demand innovative and reliable patterning methods. Through the integration of cutting-edge materials, sophisticated metrology, and inspection techniques, and creative lithographic solutions like direct write, programmable masks, and multi-beam lithography, the industry is paving the way for next-generation electronic devices.

Conclusion
As semiconductor technology continues to evolve, the need for innovative solutions in advanced packaging becomes ever more critical. Technologies such as programmable masks, laser direct imaging, and maskless lithography are pushing the boundaries of traditional lithography while providing the flexibility, precision, and efficiency required for next-generation devices. These advancements enable the industry to meet the increasing demands for high-density interconnects, improved performance, and cost-effective manufacturing.

The collaborative integration of these diverse lithographic techniques, alongside sophisticated materials and metrology methods, underscores the semiconductor industry’s commitment to innovation. By addressing the challenges associated with thermal management, mechanical stress, and signal integrity, these technologies help advance patterning technology for advanced packaging.

—Ed Sperling contributed to this report.

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