Better materials and processes enable smaller, higher performing systems-in-package.
System-in-package (SiP) is quickly emerging as the package option of choice for a growing number of applications and markets, setting off a frenzy of activity around new materials, methodologies, and processes.
SiP is an essential packaging platform that integrates multiple functionalities onto a single substrate, which enables lower system cost, design flexibility, and superior electrical performance through shorter interconnections. SiPs are showing up in 5G, IoT, mobile, consumer, telecom, and automotive apps. Of these, the largest and perhaps most exciting segment is consumer and wearable packages — from smart earbuds to capacitor pain patches — slim, comfortable devices that rapidly deliver the health and fitness data people want.
In many respects, SiP and other types of advanced packaging enable the performance and cost benefits once associated almost exclusively with Moore’s Law. “Through our fan-out combinations, flip-chip, BGA, and embedded solutions, ASE has worked really hard, together with TSMC, to extend the Moore’s Law criteria where we hopefully double performance — maybe not at half the cost, but with a cost benefit,” said Yin Chang, senior vice president of sales and marketing at ASE. “That’s why we introduced the VIP Platform to provide a toolbox of solutions that give architects the highest level of flexibility to create differentiated systems.”
Others agree that advanced packaging plays a key role in improving system performance. “At the end of the day, system-level performance is all that matters,” said David Fried, president of Coventor, part of Lam Research. “We are still pushing up against the power, performance, power, area and cost (PPAC) barriers. We are just pushing on different parameters to keep enhancing system-level performance for as long as the market keeps demanding that we provide additional compute power and memory.”
Package type selection typically comes down to balancing performance and cost. “Flip-chip dominates the RF AiP mmWave market, but there is a trend to develop fan-out AiPs (antenna in packages),” said Stefan Chitoraga, technology and market analyst for Yole Intelligence. “Fan-out advantages include smaller form factor, leveraging high-density RDL, and fine pitch compared to flip-chip. Nevertheless, fan out is still too costly, and there are technical challenges to overcome.”
Such challenges include die shift and warpage, which are being addressed by various tooling and process modifications. [1]
To enable high performance, efficiency, and low cost in a single SiP, engineers are incorporating new molding materials, double-sided SiPs, laser-assisted bonding (LAB), and next-generation flexible substrates in fan-out, flip chip, and embedded SiPs.
SiP in 3D
SiP is part of the industry’s 3D revolution. Along with trends to accommodate more I/Os in finer pitches, there are a number of other efforts to cram more into a package rather than onto a single die. This includes multiple redistribution layers in fan-outs, bridges and interposers to connect different die together, double-sided packages to increase density, and embedded die options to enable faster die-to die processing in smaller profiles that consume less power.
SiPs today combine a variety of components, from GPUs and RF ICs, to memories, sensors, passives, and much more. “ASE’s SiP technology supports the integration of different microcontrollers, ASICs, antennas, and sensors that control all the functions in a continuous glucose monitor (CGM), for instance,” according CP Hung, vice president, Corporate R&D at ASE.
Hung also described a redesign of multiple sensors in a quad-flat no-leads (QFN) package to a wafer-level chip-scale package (WL-CSP) with through-silicon vias, which can improve electrical performance by 80% while reducing its footprint by 30%. Hung said there also are biometric applications for SiP, including in-vitro diagnostics with microfluidic channels for testing blood, SiP-based hearing aids, and wafer-level SiP for sensor hubs that have a 77% smaller footprint than traditional packaging.
SiPs also shake up the supply chain and cost structures. “You see this every day with cell phones. They are getting thinner, lighter, while performing more functions, but that requires that the packaging keeps pace with these designs, which means maintaining signal integrity, managing thermal issues, reducing interference, etc.,” said Sam Sadri, senior process engineer at QP Technologies. “But where there are challenges, there are solutions. With flip-chip, you try to get rid of the heat from the bottom when you do die attach, so you use a heat sink and thermal grease at the interface. I’ve seen 3D substrates with piping and coolant running through it.”
In addition to evaluating all the process and configuration options within SiP, Sadri emphasized a growing concern over IP protections in systems.
Fig. 1: The SiP manufacturing market is split among leading OSATs and foundries. Source: Yole Intelligence
Yole analysts estimate the SiP market will grow at a 5% CAGR to $19 billion in 2025, up from a base of $13.8 billion in 2020 (see figure 1). Market leaders are ASE, Sony, Amkor, JCET, and TSMC. Some 85% of the market is mobile and consumer products, followed by telecom and infrastructure, then automotive packages.
In addition, SiP I/O pitch is expected to tighten its range from 90-350µm today to 80-90µm by 2025. “In flip-chip and wire bond SiP, substrate SAP (semi-additive process) panel is used in combination with embedded silicon bridge using copper pillars, or silicon interposer using TSVs and microbumps,” said Chitoraga.
SiPs encompasses several assembly approaches, including flip-chip and wire bond SiPs (the largest in revenue and units), followed by fan-out WLP, then embedded-die packages. “SiP give system designers the flexibility to mix and match IC technologies, optimize performance of each functional block, and reduce cost,” said Gabriela Pereira, technology and market analyst at Yole Intelligence. “Fully integrated SiP solutions enable designers to implement additional functionalities like Bluetooth or camera modules into a system with minimal design effort.”
A prototype wireless earbud capable of measuring body temperature and taking an electrocardiogram (ECG) is one recent example of a wearable device being developed by ASE and one of its customers (see figures 2). [3] Kueihao Tseng and colleagues at ASE highlighted the fact that the working electronics, packaging, and testing framework reside near the outside of the earbud, with connections through pogo pins in a round PCB. This approach improves signal integrity and enables component replacement. The engineers optimized the molding process and metallic polymer material for low resistance (<0.05Ωm), while remaining flexible for comfortable fit.
Fig. 2: The 3D SiP module on a flexible substrate connects the conductive electrode to temperature sensor to SiP module to round PCB in this smart earbud. Source: ASE
On the flexible printed circuit, a signal processing IC and passive components convert mV-level biofeedback signals to digital signal. The earbud measures temperature with a thermistor, which is less expensive than an IR LED. With process modifications, the ECG waveform was able to match the Apple watch benchmark (see figure 3).
Fig. 3: Electrocardiogram results using the prototype earbud correlate with the Apple watch benchmark. Source: ASE
Evolving processes
There are several main options for connecting die bumps to substrate pads. Among them:
“For chiplet applications, laser-assisted bonding works really well, as long as the die size doesn’t get too large,” said ASE’s Chang. “For much larger die, thermocompression bonding provides even heating and pressure across the large area.”
LAB was developed by Amkor engineers in 2014 and has been used in assembly lines since 2018 for flip-chip packaging. Amkor currently is developing a next-generation LAB technology that especially targets interconnection with thermal interface materials (TIMs) in high-performance packages.
“Recently, demand for fine-pitch flip chip bumps and large/thin substrate packages has increased, resulting in industry interest in LAB due to its good quality and high productivity,” according to SeokHo Na, director of Amkor Technology Korea.” [2] TIMs help dissipate heat from the die to lid in flip-chip BGAs using conductive interfaces such as gold. But the silicon die with a gold surface tends to reflect much of the laser directed at it, leading to non-wet failures with traditional LAB.
The advanced LAB process instead directs the laser at the package backside through the tool’s stage vacuum block. The engineers adjusted the process conditions, including power and time of exposure, to form more reliable copper pillar bumps with SnAg tips. Amkor noted that in comparison with mass reflow, LAB is less likely to produce solder sidewall creep (wicking) and associated with mass reflow and accommodates finer bump pitches. Other architectures, such as 2.5D and 3D HBMs (in EMC), are likely to take advantage of LAB, as well. “Next-gen LAB may be the only solution for fine-pitch bump devices with backside metal (TIM) die,” concluded Na.
Embedded SiP
Embedded SiP is a rapidly evolving market. In a recently developed 3D embedded power SiP, the molding compound (EMC) was the greatest concern. A feature of the platform is the EMC fill process around power FETs sandwiched between substrates. [4] The EMC had to meet specific parameters of Young’s modulus (stretch) and glass transition temperature (flow) to minimize package warpage — especially important in power transistors because they cannot reap the benefits of Moore’s Law scaling. Warpage was simulated using Ansys’ full finite element model software.
Fig. 4: By switching from laminate substrate to leadframe-based processes with optimized thermocompression bonding and molding material, a more compact embedded SiP using single-sided cooling is possible. Source: Amkor
Byron Jin Kim, senior director at Amkor Technology Korea, and his team compared thermal results using ICEPAK software for the embedded SiP with a dual-cooled IGBT on direct-bonded copper-on-ceramic substrate with three embedded structures (see figure 4). The embedded process of choice (d) uses die attach on the bottom substrate, and requires only single-sided cooling. The team determined the leadframe-based process module demonstrated superior thermal performance than the design with laminated substrates. In addition, the core ball placement is important.
“Cu core ball was performed on top substrate by the process of flux printing-ball placement-reflow. This approach was key to controlling proper solder wetting in the process parameter set-up,” the report stated. Going forward, Amkor anticipates a variety of embedded SiP options for similar systems, including power circuits with half-bridge and full-bridge applications.
Fig. 5: Thermocompression bonding process shows die and copper ball placement (a), copper core ball wetting shows the routable Microleadframe at angle (b), and the package’s side view prior to molding (c). Source: Amkor
Antenna in package
For 5G and 6G, antenna technology is challenging. Instead of a single antenna, there are phased arrays of antennas, because at mmWave and terahertz (THz) frequencies long paths from semiconductor packages to antennas lead to high losses. That makes it desirable to integrate these antennas into the SiP.
“Before 2018, LGA SiPs were used in the RF industry, but BGA has since been widely adopted thanks to the development of double-sided packaging,” said Yole’s Pereira. “Players like Broadcom, Qorvo, and Skyworks implement stepwise innovations with solutions like DSBGA and DS-MBGA (double-sided molded BGA), whereas Murata directly implemented DS-MBGA for system integration and miniaturization. The Integrated Fan-Out Antenna in Package (InFO_AiP) from TSMC is another innovative solution waiting to be used, but it has been delayed because of cost inefficiency.”
In addition to different package types, substrates for high-frequency uses are changing. Traditional PCB materials cannot meet the needs of 5G’s terahertz frequencies because of high dielectric loss and water absorption. The industry currently is evaluating various liquid crystal polymer (LCP) substrates for their electrical properties, hermeticity and material flexibility.
“We are always trying to find the balance between signal strength and signal loss, and as far as 5G, we are looking at a lot of different material sets, different LCP integrations,” said Chang. “Hopefully that minimal loss solution will simplify the overall AiP design.”
Conclusion
Packaging houses and foundries are pursuing a variety of SiPs to meet the different needs among mobile consumer, communications and infrastructure, and automotive applications. To reduce cost and improve manufacturing reliability, new materials and processes are being added for flip chip, fan-out, and embedded SiPs. But the moving target associated with maintaining signal integrity, transferring more data faster, and overcoming tooling/substrate limitations will continue to encourage next-gen innovation.
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System-In-Package Thrives In The Shadows
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