tag: IR drop

PDN Challenges In DRAM-Based Compute-In-Memory Systems (UT Austin)
By Technical Paper Link - 11 Apr, 2026 - Comments: 0

A new technical paper, "A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM," was published by researchers at UT Austin. Abstract "Compute-in-memory (PIM) mitigates the memory wall by performing computation within memory, reducing data movement and improving energy efficiency. DRAM-based PIM is particularly attractive due to its high density, matu... » read more

Robust Dynamic Voltage Droop Mitigation And Power Management
By Graham Woods - 13 Jan, 2026 - Comments: 1

Power management is one of the keys for developing successful semiconductors products. There are virtually no applications for which power consumption is not a concern. Many creative solutions have been developed to reduce and manage power. Making these schemes work robustly in real-world conditions can be a challenge. This post considers widely used methods—voltage droop/glitch detection and... » read more

Minimizing Design Risk: Rapid Feasibility Exploration For Multi-Die Designs
By Synopsys - 23 Dec, 2025 - Comments: 0

Multi-die design is revolutionizing semiconductor innovation, offering unprecedented flexibility, but also introducing complexity. What if designers could spot and solve critical issues, such as IR drop, electromigration, and thermal impact before they ever reach the design implementation stage? In this white paper, we explore how rapid, comprehensive feasibility exploration enables desi... » read more

Minimizing Voltage Loss And Improving Yield In Advanced GAA Chips
By Qingpeng Wang - 18 Dec, 2025 - Comments: 0

The problem: As metal pitch scaling shrinks to support the next generation of logic devices, the IR (or voltage) drop from conventional frontside connections has become a major challenge [1,2]. As electricity travels through a chip’s metal wiring, some voltage gets lost because wires have resistance. If the voltage drops too much, the chip’s transistors can’t get enough power and ... » read more

Noise: A Chip Killer
By Brian Bailey - 13 Nov, 2025 - Comments: 0

Noise has always been important to communications experts, but it's quickly becoming an issue that every semiconductor designer has to contend with. Some chips already have been compromised. Noise can be defined as any deviation from the ideal that can impact intended functionality. When it comes to semiconductors, that could mean the ability to reliably extract a signal value at the intende... » read more

Power Integrity And Voltage Issues Get Harder To Detect And Solve
By Ann Mutschler - 13 Nov, 2025 - Comments: 0

Voltage and power integrity are becoming increasingly critical and challenging for chip designers and architects, regardless of which process technology they are using or which market they are targeting. An explosion of features vying unevenly for current is increasing the number of constraints and possible interactions that engineers need to sort through to ensure reliability. These include... » read more

The Demise Of Static Timing Verification?
By Brian Bailey - 11 Sep, 2025 - Comments: 0

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address these problems? Static timing verification (STA) was a cornerstone technology for the acceptance of the register transfer level (RTL) abstraction. It showed that functionality would not be impa... » read more

Same Chip, Two Destinies: How Power Profiles Improve With On-Chip Monitoring
By Eyal Fayneh - 09 Sep, 2025 - Comments: 0

What happens to critical power-related considerations when the same chip is handled two different ways, with or without visibility from within? This article begins by examining how the absence of on-chip monitoring impacts peak power, average power, and Di/Dt noise (rate of current change), as illustrated in the diagram below and the subsequent discussion. It then details how these aspects c... » read more

Machine Learning-Based IR Drop Prediction Approach
By Technical Paper Link - 25 Feb, 2025 - Comments: 0

A new technical paper titled "Estimating Voltage Drop: Models, Features and Data Representation Towards a Neural Surrogate" was published by researchers at KTH Royal Institute of Technology and Ericsson Research. ABSTRACT "Accurate estimation of voltage drop (IR drop) in modern Application-Specific Integrated Circuits (ASICs) is highly time and resource demanding, due to the growing complex... » read more

Power Delivery Challenges in 3D HI CIM Architectures for AI Accelerators (Georgia Tech)
By Technical Paper Link - 07 Feb, 2025 - Comments: 0

A new technical paper titled "Co-Optimization of Power Delivery Network Design for 3D Heterogeneous Integration of RRAM-based Compute In-Memory Accelerators" was published by researchers at Georgia Tech. Abstract: "3D heterogeneous integration (3D HI) offers promising solutions for incorporating substantial embedded memory into cutting-edge analog compute-in-memory (CIM) AI accelerators, ad... » read more

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