tag: Synopsys

Blog Review: June 23
By Jesse Allen - 23 Jun, 2021 - Comments: 0

Synopsys' Manuel Mota shows how splitting SoCs into smaller dies for advanced packaging and using die-to-die interfaces to enable high bandwidth, low latency, and low power connectivity can benefit hyperscale data centers. Siemens EDA's Chris Spear explains the relationship between classes and objects in SystemVerilog with a handy visualization and notes the difference between SystemVerilog ... » read more

Debugging Point-to-Point Resistance Using Contribution By Layer In IC Validator PERC
By Synopsys - 23 Jun, 2021 - Comments: 0

PERC Point-to-point resistance (P2P resistance) functionality is a crucial EDA technology to enable complex P2P effective resistance measurement along ESD paths in automation for foundry qualified ESD/Latch-up checker or in-house custom checker. This technology is applied to the entire chip, block, and IP designs on cell or transistor level layout database. Since the ESD path count could grow t... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 18 Jun, 2021 - Comments: 0

Automotive U.S. electric truck manufacturer Lordstown Motors has an electric truck but after a large buyer fell through, it admitted it does not have any firm orders on its trucks, according to an AP story. The CEO and CFO resigned earlier this week. The electric car company Canoo announced its US manufacturing facility will be in Oklahoma. Cadence revealed its Tensilica FloatingPoint DSP (... » read more

Shifting Toward Data-Driven Chip Architectures
By Ed Sperling and Ann Mutschler - 16 Jun, 2021 - Comments: 0

An explosion in data is forcing chipmakers to rethink where to process data, which are the best types of processors and memories for different types of data, and how to structure, partition and prioritize the movement of raw and processed data. New chips from systems companies such as Google, Facebook, Alibaba, and IBM all incorporate this approach. So do those developed by vendors like Appl... » read more

Blog Review: June 16
By Jesse Allen - 16 Jun, 2021 - Comments: 0

Arm's Adrian Herrera explores the latest version of AMBA ATP Engine, an open-source implementation of the AMBA Adaptive Traffic Profiles (ATP) synthetic traffic framework specification, which adds the ability to program AMBA ATP traffic generation from Linux environments. Cadence's Paul McLellan finds out just how effective glitching chips is by delivering incorrect voltages and clock freque... » read more

Targeting Redundancy In ICs
By Brian Bailey - 14 Jun, 2021 - Comments: 0

Technology developed for one purpose is often applicable to other areas, but organizational silos can get in the way of capitalizing on it until there is a clear cost advantage. Consider memory. All memories are fabricated with spare rows and columns that are swapped in when a device fails manufacturing test. "This is a common method to increase the yield of a device, based on how much memor... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Jun, 2021 - Comments: 0

Siemens Digital Industries Software acquired Pro Design's proFPGA product family of FPGA desktop prototyping technologies. Through a prior OEM relationship, proFPGA technology is already part of the Xcelerator portfolio; Siemens noted that the acquisition will allow for fuller integration with its Veloce hardware-assisted verification system. Pro Design will continue to operate as an independen... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 11 Jun, 2021 - Comments: 0

Pervasive computing — IoT, edge, cloud, data center, and back Xilinx introduced its Versal AI Edge series of adaptive SoCs, or adaptive compute acceleration platforms (ACAPs), that can be manage AI-ML workloads in edge applications. The chip is designed for flexible, low latency, edge applications where algorithms may need updating. The software programmable chips have an AI Engine-ML featur... » read more

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP
By Gary Ruggles - 10 Jun, 2021 - Comments: 0

PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This article provides designers a summary of the major changes and how they can be handled to ensure a smooth and successful transition to PCIe 6.0. The three major changes in PCIe 6.0 that designers nee... » read more

Thermal Floorplanning For Chips
By Brian Bailey - 10 Jun, 2021 - Comments: 0

Heat management is becoming crucial to an increasing number of chips, and it's one of a growing number of interconnected factors that must be considered throughout the entire development flow. At the same time, design requirements are exacerbating thermal problems. Those designs either have to increase margins or become more intelligent about the way heat is generated, distributed, and dissi... » read more

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