tag: Synopsys

Dependent Failure Analysis For Safety-Critical IP And SoCs
By Shivakumar Chonnad - 02 Nov, 2020 - Comments: 0

By Shivakumar Chonnad, Radu Iacob, and Vladimir Litovtchenko Due to the increased complexity in safety-critical system hardware, software, and mechatronics, the functional safety development process must address systematic and random hardware failures. Numerous safety-related activities are performed during safety-critical IP and SoC developments, as part of the safety lifecycle, from produc... » read more

Week In Review: Design, Low Power
By Jesse Allen - 30 Oct, 2020 - Comments: 0

M&A AMD will acquire Xilinx for $35 billion in an all-stock deal. "Joining together with AMD will help accelerate growth in our data center business and enable us to pursue a broader customer base across more markets,” said Victor Peng, Xilinx president and CEO. The deal is expected to close by the end of 2021. The acquisition of the programmable logic giant will leave only a few purepla... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 30 Oct, 2020 - Comments: 0

Automotive Synopsys added support for Infineon's automotive AI chip, the AURIX TC4xx 32-bit microcontroller with parallel processing unit. Dialog Semiconductor announced automotive qualification for its DA7280 high-definition haptic driver. The company Alps Alpine is using the DA7280 in Alps Alpine Heavy, the latest version of its HAPTIC Reactor Linear Resonant Actuators (LRAs). Bosch, M... » read more

Making IC Test Faster And More Accessible: Part 1
By Robert Ruiz - 30 Oct, 2020 - Comments: 0

The fundamental challenges of IC test have been the same for a long time. At the heart of all test strategies is controllability and observability. First, control the state of the chip with known test vectors and then observe the chip to determine if it exhibits good or faulty behavior. There have been many innovations over the years to make the required testing of chips more tractable. Thanks ... » read more

A Renaissance For Semiconductors
By Brian Bailey - 29 Oct, 2020 - Comments: 2

Major shifts in semiconductors and end markets are driving what some are calling a renaissance in technology, but navigating this new, multi-faceted set of requirements may cause some structural changes for the chip industry as it becomes more difficult for a single company to do everything. For the past decade, the mobile phone industry has been the dominant driver for the semiconductor eco... » read more

A Machine Learning-Based Approach To Formality Equivalence Checking
By Avinash Palepu - 29 Oct, 2020 - Comments: 0

By Avinash Palepu, Namrata Shekhar and Paula Neeley After a long and hard week, it is Friday night and you are ready to relax and unwind with a glass of wine, a sumptuous dinner and a great movie. You turn on Netflix and you expect that it will not only have plenty of pertinent suggestions for you, but also the most appropriate one based on all the previous movies and shows that you have wat... » read more

Is Hardware-Assisted Verification Avoidable?
By Brian Bailey - 29 Oct, 2020 - Comments: 1

Emulation is emerging as the tool of choice for complex and large designs, but companies that swap from simulation to emulation increasingly recognize this is not an easy transition. It requires money, time, and effort, and even then not everyone gets it right. Still, there are significant benefits to moving from simulation to emulation, providing these systems can be utilized efficiently en... » read more

Blog Review: Oct. 28
By Jesse Allen - 28 Oct, 2020 - Comments: 0

Synopsys' Jacob Wilson provides some tips for how to prepare for the upcoming ISO SAE 21434 cybersecurity standard for road vehicles, starting with a security plan and understanding of risk levels. Cadence's Paul McLellan checks out Arm's first face-to-face wafer-bonded design, why it might be desirable, and some important aspects of how the proof-of-concept was developed. In a video, Men... » read more

Lower Process Nodes Drive Timing Signoff Software Evolution
By Synopsys - 28 Oct, 2020 - Comments: 0

A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

Performance and Power Tradeoffs At 7/5nm
By Ed Sperling - 27 Oct, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

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