Blog Review: Feb. 6


Mentor's Harry Foster examines the impact of growing design complexity on how long designs spend in verification, the ratio of design to verification engineers on a project, and how they spend their time. Cadence's Paul McLellan checks out some of the emerging memory technologies and notes there's no clear indication which will dominate the market. Synopsys' Meenakshy Ramachandran checks ... » read more

MISing In Signoff


Timing signoff is critical to ensure your design will perform as expected before it is taped out. For many designs, signoff and subsequent ECOs are focused on the performance target and iterating to meet that.  Once the performance goals are met then the attention passes onto hold-time fixing and then, usually, quickly onto tapeout.  However, even after extensive signoff analysis, silicon fai... » read more

Using Memory Differently


Chip architects are beginning to rewrite the rules on how to choose, configure and use different types of memory, particularly for chips with AI and some advanced SoCs. Chipmakers now have a number of options and tradeoffs to consider when choosing memories, based on factors such as the application and the characteristics of the memory workload, because different memory types work better tha... » read more

EDA Grabs Bigger Slice Of Chip Market


EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Blog Review: Jan. 30


Cadence's Paul McLellan provides a primer on embedded memory types, their tradeoffs, and the emerging technologies to keep an eye on. Mentor's Matthew Ballance takes a look at how Portable Stimulus can help create better virtual sequences. Synopsys' Taylor Armerding takes a look at what the next year holds for open source, from changes in license terms to the impact of GDPR and a broader ... » read more

A Simplified Way to Debug IIP Designs and SoC


Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. It's not uncommon for an engineer to run the verification test on what appears to be the main design problem, only to find the problem in the dump. Traditional debug techniques don't always help to localize the issue. This whitepaper... » read more

Week In Review: Design, Low Power


M&A Ansys will acquire Helic, a provider of electromagnetic crosstalk analysis and signoff tools. Founded in 2000, Helic's tools included pre- and post-LVS EM modeling, inductor synthesis and modeling, and analysis of crosstalk risk. The company's technology will be integrated into a solution for on-chip, 3D integrated circuit and chip-package-system electromagnetics and noise analysis. Th... » read more

Week in Review: IoT, Security, Auto


Internet of Things Tony Franklin, Intel’s general manager for Internet of Things Segments, is interviewed by Lorin Fries on how the chipmaker is helping to develop smart farming applications. “We focus primarily on high-performance computer technologies, as well as communication technologies, which have great applicability for food systems. We work closely with a broad ecosystem of partner... » read more

Variation Issues Grow Wider And Deeper


Variation is becoming more problematic as chips become increasingly heterogeneous and as they are used in new applications and different locations, sparking concerns about how to solve these issues and what the full impact will be. In the past, variation in semiconductors was considered a foundry issue, typically at the most advanced process node, and largely ignored by most companies. New p... » read more

Blog Review: Jan. 23


Synopsys' Taylor Armerding investigates what's happened with the Stuxnet malware since 2010, when it destroyed hundreds of centrifuges at an Iranian nuclear enrichment facility. Cadence's Paul McLellan provides an update on the current state of EUV and what's needed to make high-volume manufacturing possible. In a video, Mentor's Colin Walls explains software's role in embedded system pow... » read more

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