tag: Synopsys

Blog Review: Aug. 6
By Ed Sperling - 06 Aug, 2014 - Comments: 0

Mentor’s Colin Walls takes a look at bad behavior—the undefined kind that you get from doing C programming wrong and adding too much complexity up front. Cadence’s Brian Fuller interviews his colleague about what engineers need to know in regards to finFETs, advanced nodes and parasitic extraction. Short answer: Plenty. Synopsys’ Mick Posner is building FPGA prototype boards and... » read more

Leveraging Processor Extensibility To Build An Ultra Low-Power Embedded Subsystem
By Synopsys - 06 Aug, 2014 - Comments: 0

There is increasing demand for electronic devices to execute more functions while consuming less power and silicon area. To achieve this, systems instantiating multiple, heterogeneous processor cores optimized for low power and high performance are gaining popularity among design teams. In these systems, one or more deeply embedded processors execute a limited set of dedicated applications. The... » read more

Blog Review: July 30
By Ed Sperling - 30 Jul, 2014 - Comments: 0

Mentor’s Colin Walls looks at a free collaborative online tool called codepad, which can be used for compiling, interpreting and executing code quickly. Free is good—sometimes. Cadence’s Brian Fuller followed a recent panel on high-speed, cross-fabric interface design, which focused on why designers need to consider chip, package and board to ensure signal and power integrity. So what... » read more

IP Integration Challenges Rising
By Ann Mutschler - 24 Jul, 2014 - Comments: 0

It’s not just [getkc id="80" comment="lithography"] that is putting a crimp in sub-28nm designs. As more functions, features, transistors and software are added onto chips, the pressure to get chips out the door has forced chipmakers to lean more heavily on third-party IP providers. Results, as you might expect, have been mixed. The number of blocks has mushroomed, creating its own web of ... » read more

EDA’s Hedge Plays
By Ed Sperling - 24 Jul, 2014 - Comments: 0

While 14/16nm process technologies with finFETs and double patterning have pushed complexity to new heights, the move to 10nm fundamentally will change a number of very basic elements of the design through manufacturing flow—and EDA vendors will be caught in the middle of having to make hard choices between foundries, processes, packaging approaches, and potentially which markets to serve. ... » read more

Planning For The Unexpected
By Tom De Schutter - 24 Jul, 2014 - Comments: 0

Last month we undertook a big family trip. My parents, my brother and his family came from Belgium to California, and together we embarked on a trip across the Northwest United States. Starting in Silicon Valley we drove via Lake Tahoe and Salt Lake City to Yellowstone. Afterward, we crossed over to Seattle and Portland to finish off the trip with visits to Crater Lake and Lassen Volcanic Natio... » read more

Reversing Course, With A Twist
By Brian Bailey - 24 Jul, 2014 - Comments: 1

Semiconductor Engineering is running an extended series of articles that examine the assertion that the end of Moore’s Law will have profound implications for the entire semiconductor, EDA and IP industries. Part one of this article, which focuses on the EDA industry, addressed the question about who was going to pay for future development of EDA tools for the latest production nodes. The ind... » read more

Blog Review: July 23
By Ed Sperling - 23 Jul, 2014 - Comments: 0

Mentor’s John Day says that within the decade you will be able to contact a real person from your car. Hopefully that doesn't mean marketing people will be able to contact you while you’re stuck in traffic. Cadence’s Brian Fuller says the future of EDA in the automotive market isn’t just about chips. Think security, software and cost reduction. It’s not just SoCs that are going ... » read more

More Effective Test: Slack-Based Transition Delay
By Synopsys - 23 Jul, 2014 - Comments: 0

Semiconductor companies have come to rely on delay testing to attain high defect coverage of manufactured digital integrated circuits (ICs). Delay testing uses transition delay (TD) patterns created by automatic test pattern generation (ATPG) tools to target subtle manufacturing defects in fabricated designs. Although standard TD testing improves defect coverage beyond levels stuck-at patterns ... » read more

Where Do We Stand With CDC?
By Ann Mutschler - 18 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of Arteris; Shaker Sarwary, VP of Formal Verification Products at Atrenta; Pranav Ashar, CTO at Real Intent; and Namit Gupta, CAE, Verification Group at Synopsys. What follows are excerpts of that conversation. SE: What are the biggest use models for CDC verification today... » read more

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