tag: Synopsys

DFM And Multipatterning
By Ed Sperling - 17 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss DFM at advanced nodes with Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics; Jongwook Kye, lithography modeling and architecture fellow at GlobalFoundries; David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics; Ya-Chieh Lai, engineering director for DFM/CLS silicon signoff and ver... » read more

The Week In Review: Design
By Ed Sperling - 17 Jul, 2014 - Comments: 0

Tools Cadence unveiled two new tools. The first is a rapid prototyping platform that the company claims will shorten bring-up time by 70%, with 4X improvements in capacity, with IEEE 1801 support for low-power verification through its emulation platform. The second is a single and multi-corner custom/analog extraction tool, which it claims will improve performance by 5X. The tool has been cert... » read more

Blog Review: July 16
By Ed Sperling - 16 Jul, 2014 - Comments: 0

Mentor’s Scott Salzwedel describes a conversation that could very well happen in the future and it raises an interesting idea. As medical electronics proliferate, will emergency medical teams need to include out systems engineers? Cadence’s Brian Fuller has a summer engineering project that resembles the Bridge Over the River Kwai. He should win an Oscar for this one. Ansys’ Bill ... » read more

The Week In Review: Design
By Ed Sperling - 11 Jul, 2014 - Comments: 0

M&A CEVA bought RivieraWaves, which makes IP for WiFi and Bluetooth connectivity. CEVA said the deal will boost its market to 35 billion connected devices within six years. The two companies have been collaborating in the WiFi market for the past couple of years. Total cost of the deal is $19 million. Mentor Graphics acquired XS Embedded GmbH, a German-based developer of automotive-read... » read more

After Moore’s Law: More With Less
By Brian Bailey - 10 Jul, 2014 - Comments: 6

In the decades when Moore’s Law went unquestioned, the industry was able to migrate to the next smaller node and receive access to more devices that could be used for increased functionality and additional integration. While less significant transistor-level power savings have been seen from the more recent nodes, as leakage currents have increased, the additional levels of integration have b... » read more

Raising The Abstraction Of Power: Trends
By Ann Mutschler - 10 Jul, 2014 - Comments: 0

Given that design requirements for today’s SoCs go well beyond performance and area, energy efficiency and its impact on system design plays a major role for many end applications ranging from wireless sensor networks to autonomous vehicles as well as emerging applications in the Internet of Things market segment, where cooling capability is limited and expensive. For these reasons, a comp... » read more

Supporting LP In New Process Nodes
By Ann Mutschler - 10 Jul, 2014 - Comments: 0

Manufacturing process nodes and EDA tools are advancing all the time, but not always utilized at the same pace. And from a tools perspective, there are challenges to supporting low power in new process nodes while maintaining and improving the existing process nodes. One way design teams address this is by leveraging the most advanced software on the less-than-bleeding edge designs. To th... » read more

Using PCI Express L1 Sub-states To Minimize Power Consumption In Advanced Process Nodes
By Rita Horner - 10 Jul, 2014 - Comments: 0

The major sources of Internet traffic are shifting from wired to wireless and mobile devices. With the growing regulatory requirements and increased consumer pressure for more power-efficient products, designers need to better understand and optimize the power consumption of battery-operated devices. Power consumption of a portable device widely varies based on the user’s behavior and appl... » read more

28nm FinFETs?
By Brian Bailey - 10 Jul, 2014 - Comments: 5

One star of the upcoming 14/16nm process node is the introduction of the finFET, a fundamentally new transistor that overcomes many of the limitations associated with planar transistors. While these devices are more complex to construct—and the physical extraction processes associated with them is more complex due to an increased number of resistances and capacitances—they are seen as a tra... » read more

Ultra Low-Power 9D Sensor Fusion Implementation
By Synopsys - 09 Jul, 2014 - Comments: 0

This paper presents a case study on computing the 3D orientation of a device by means of a 9D fusion algorithm. The focus is on optimizing the fusion algorithm for execution on the DesignWare Sensor IP Subsystem. Performance measurements show the benefits of using ARC Processor EXtension (APEX) accelerators, which improve both cycle count and energy consumption in comparison to other commercial... » read more

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