tag: SystemC

Formally Verifying SystemC/C++ Designs
By Rob van Blommestein - 29 Jul, 2021 - Comments: 0

We’re seeing an increase in the number of designs employing SystemC/C++. This isn’t surprising given the fact that specific use models have emerged to drive common design flows across engineering teams leading to the adoption of high-level synthesis (HLS) at many large semiconductor and electronic systems companies. These HLS tools are a popular method to rapidly generate design components ... » read more

Dynamic Fault Injection Into Digital Twins Of Safety-Critical Systems
By Fraunhofer IIS/EAS - 07 Jul, 2021 - Comments: 0

In this work we present a technology for dynamically introducing fault structures into digital twins without the need to change the virtual prototype model. The injection is done at the beginning of a simulation by dynamically rewiring the involved netlists. During the simulation on a real-time platform, faults can be activated or deactivated triggered by sequences, statistical effects or by ev... » read more

Virtual Prototyping In SoC Development
By Christoph Sohrmann - 21 Jun, 2021 - Comments: 0

Modern semiconductor technologies enable manufacturers to pack more and more functions and memory into a single silicon die. While steadily advancing microintegration based on Moore’s Law just a few years ago mainly focused on increasing the clock frequency of integrated circuits (IC), today, it’s the design complexity and number of blocks that enable new IC functions. More and more logic b... » read more

Continuing Challenges For Open-Source Verification
By Brian Bailey - 01 Jun, 2021 - Comments: 1

Experts at the Table: This is the last part of the series of articles derived from the DVCon panel that discussed Verification in the Era of Open Source. It takes the discussion beyond what happened in the panel and utilizes some of the questions that were posed, but never presented to the panelists due to lack of time. Contributing to the discussion are Ashish Darbari, CEO of Axiomise; Serge L... » read more

Formal Solutions For SystemC/C++ Verification
By OneSpin Solutions - 23 Sep, 2020 - Comments: 0

OneSpin Solutions provides its popular 360 DV formal verification product line, which allows for both the automated checking and full assertion-based verification of SystemC/C++ design representations. This solution extends the verification capability that may be applied to abstract designs, coded in SystemC/C++ for many different use models. This white paper describes the OneSpin solution a... » read more

Fused: Closed-Loop Performance And Energy Simulation Of Embedded Systems
By Arm - 08 Jul, 2020 - Comments: 0

Energy-driven computing is an emerging paradigm that aims to fuel the proliferation of tiny and low-cost IoT sensing and monitoring devices. Energy-driven computers are generally powered by energy harvesting sources, and adapt their operation at runtime according to energy availability; thus, they must be designed and tested according to the expected dynamics of their power source. However, tod... » read more

New Ways To Optimize Machine Learning
By Bryon Moyer - 02 Apr, 2020 - Comments: 1

As more designers employ machine learning (ML) in their systems, they’re moving from simply getting the application to work to optimizing the power and performance of their implementations. Some techniques are available today. Others will take time to percolate through the design flow and tools before they become readily available to mainstream designers. Any new technology follows a basic... » read more

Software-Defined Hardware Gains Ground — Again
By Ann Mutschler - 26 Mar, 2020 - Comments: 0

The traditional approach of running generic software on x86-based CPUs is running out of steam for many applications due to the slowdown of Moore’s Law and the concurrent exponential growth in software application complexity and scale. In this environment, the software and hardware are disparate due the dominance of the x86 architecture. “The need for and advent of the hardware accelerat... » read more

Speeding Up Verification Using SystemC
By Ed Sperling - 23 Mar, 2020 - Comments: 0

Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation. » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 28 Feb, 2020 - Comments: 0

AI/Edge The United States Department of Defense (DOD) has adopted ethical principles for using artificial intelligence in warfare that chiefly say the U.S. has to follow the laws, treaties, in use of AI in warfare. Any AI used by DOD has to be responsible, equitable, traceable, reliable and governable. “The Department will design and engineer AI capabilities to fulfill their intended functio... » read more

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