tag: BiST

Balancing The Cost Of Test
By Brian Bailey - 23 Oct, 2014 - Comments: 0

As semiconductor devices became larger and more complex, the cost of [getkc id="174" kc_name="test"] increased. Testers were large pieces of capital equipment designed to execute functional vectors at-speed and the technology being used had to keep up with increasing demands placed on them. Because of this, the cost of test did not decrease in the way that other high-tech equipment did. Around ... » read more

Five Disruptive Test Technologies
By Mark LaPedus - 19 Jun, 2014 - Comments: 0

For years, test has been a critical part of the IC manufacturing flow. Chipmakers, OSATs and the test houses buy the latest testers and design-for-test (DFT) software tools in the market and for good reason. A plethora of unwanted field returns is not acceptable in today’s market. The next wave of complex chips may require more test coverage and test times. That could translate into higher... » read more

Test Challenges Grow
By Mark LaPedus - 09 Jun, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss current and future test challenges with Dave Armstrong, director of business development at Advantest; Steve Pateras, product marketing director for Silicon Test Solutions at Mentor Graphics; Robert Ruiz, senior product marketing manager at Synopsys; Mike Slessor, president of FormFactor; and Dan Glotter, chief executive of Optimal+. SE: In our l... » read more

Improve Logic Test With A Hybrid ATPG/BIST Solution
By Various Writers - 14 Nov, 2013 - Comments: 0

Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a passionate debate between some DFT practitioners about which is the best test method— ATPG or BIST. ATPG has been dominant for years, and is now used for full-chip test across the electronics indu... » read more

Blog Review: Sept. 11
By Ed Sperling - 11 Sep, 2013 - Comments: 0

By Ed Sperling Synopsys’ Eric Huang has unearthed the weirdest USB video ever produced—a dancing USB lighter. The messaging is pretty bizarre, too. Cadence’s Brian Fuller takes a whirlwind tour of the engineering accomplishments for the week. Check out the T-shirt message. Clearly they’re not talking about semiconductor engineers. Mentor’s Colin Walls looks at the Lua scripting... » read more

Experts At The Table: Automotive Electronics
By Ann Mutschler - 25 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss the opportunities in automotive electronics with Alexandre Palus, principal SoC architect at Altera; Aveek Sarkar, VP of product engineering & support at Apache; Mladen Nizic, engineering director, mixed signal solution at Cadence; and Stephen Pateras, product marketing director, silicon test solutions at Mentor Graphics. Wh... » read more

3D Brings Test Into Fashion
By Ann Mutschler - 16 May, 2013 - Comments: 0

By Ann Steffora Mutschler As integral and critical as test is to the success of an SoC, it isn’t always one of those topics in semiconductor design that seems fashionable. But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to... » read more

BIST For Low-Power Devices
By Steve Pateras - 09 May, 2013 - Comments: 0

By Stephen Pateras The persistent growth of mobile computing is driving an increasing need to manage power consumption within semiconductor devices. This has significant implications on the design and test of these devices. Low-power requirements affect test in two separate ways. First, it’s important to ensure that any functional power constraints are met (or at least adequately managed) du... » read more

Welcome To The ‘Probably Good Die’ Era
By Mark LaPedus - 13 Dec, 2012 - Comments: 0

By Mark LaPedus In today’s systems, consumers want more performance and bandwidth with a longer battery life. Some chip segments are keeping up with the demands. Still other areas are falling way behind the curve. Battery life is an obvious problem, but memory bandwidth is under the radar. “Initially, memory bandwidth nearly doubled every two years, but this trend has slowed over the pa... » read more

An Automated Approach To RTL Memory BIST Insertion And Verification
By Various Writers - 09 Aug, 2012 - Comments: 0

ASIC vendors have been traditionally incorporating built-in self test (BIST) and repair solutions in their customers' gate level netlist. This used to be the common industry practice for technology nodes of 65 nm and older. Designers were comfortable writing in-house Perl scripts to replace memory instances with combined memory-BIST (MBIST) instances and make necessary connections. However, for... » read more

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