tag: Cadence

RF To Millimeter-Wave Front-End Component Design Trends For 5G Communications
By Cadence - 28 Jul, 2021 - Comments: 0

This white paper discusses design challenges and solutions related to the "third wave" of communications, presenting several case studies in which the Cadence AWR Design Environment platform has been used to develop products for 5G and beyond. Examples include a multiband active antenna tuner for cellular internet of things (IoT) machine-type communications (mMTC) applications, a linear power a... » read more

Week In Review: Design, Low Power
By Jesse Allen - 23 Jul, 2021 - Comments: 0

Tools Cadence unveiled Cerebrus Intelligent Chip Explorer, a new machine learning-based tool to drive the Cadence RTL-to-signoff implementation flow. The tool aims to use reinforcement learning to find flow solutions that otherwise might not be explored and applies models to future designs. The company says it can improve productivity up to 10X and PPA up to 20% with optimization of the flow f... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 23 Jul, 2021 - Comments: 0

Security Xilinx is investing an undisclosed amount in fabless semiconductor startup Kameleon Security, which is working on a cyber protection chip for servers, data centers, and cloud computing. The proactive Security Processing Unit (ProSPU) already secures the boot and has a root of trust (RoT). The chip will be demonstrated at the Open Compute Project (OCP) Global Summit, which is planned f... » read more

Blog Review: July 21
By Jesse Allen - 21 Jul, 2021 - Comments: 0

Cadence's Paul McLellan listens in as Partha Ranganathan of Google argues that a new era of Moore's Law is emerging, defined both by the efficient design of hardware accelerators and improving the ways that hardware is utilized. Siemens EDA's Chris Spear continues exploring classes in SystemVerilog with a look at the relationship between the class variables that point to an object and how to... » read more

New Power, Performance Options At The Edge
By Heidi Elliott - 21 Jul, 2021 - Comments: 0

Increasing compute intelligence at the edge is forcing chip architects to rethink how computing gets partitioned and prioritized, and what kinds of processing elements and memory configurations work best for a particular application. Sending raw data to the cloud for processing is both time- and resource-intensive, and it's often unnecessary because most of the data collected by a growing nu... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Jul, 2021 - Comments: 0

Tools Andes Technology certified Imperas reference models for the complete range of Andes IP cores with the new RISC-V P SIMD/DSP extension. The reference models can be used to evaluate multicore design configuration options for SoC architecture exploration and support early software development before silicon prototypes are available. Cadence's digital full flow was optimized and certified... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 16 Jul, 2021 - Comments: 0

Security A new security annotation standard for hardware IP is now available for download at no cost. The board of directors of the Accellera Systems Initiative, the non-profit EDA- and IP-standards organization, approved the release of the Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0. The standard, developed by Accellera’s IP Security Assurance (IPSA) Working ... » read more

Massive IoT Interop Fuels Protocol Battle
By Bryon Moyer - 15 Jul, 2021 - Comments: 0

Wireless standards are plentiful, but most are not capable of being scaled to the level of a smart city. As a result, such networks have been built application-by-application using proprietary stacks, often with non-interoperable network layers. That, in turn, has slowed the proliferation of dense wireless connectivity at scale. “In a hyper-connected world, connectivity choices are driv... » read more

Blog Review: July 14
By Jesse Allen - 14 Jul, 2021 - Comments: 0

Siemens EDA's Wei-Lii Tan considers the tradeoffs when running library characterization in the cloud and how to think about running CPUs in parallel, the cost of throughput, and runtime reductions. A Synopsys writer checks out the reduced blanking feature in HDMI 2.1, which can help reduce the transmission rate while keeping the resolution and refresh rate intact for higher resolution displa... » read more

CEO Outlook: Chiplets, Longer IC Lifetimes, More End Markets
By Ed Sperling - 14 Jul, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, longer IC lifetimes, and a spike in the number of end applications with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; an... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy