tag: Cadence

Process Variation And Aging
By Ann Mutschler - 17 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; and Naseer Khan, vice president of sales at M... » read more

Developing Smarter, Safer Cars with ADAS IP
By Cadence - 16 Jan, 2019 - Comments: 0

By Charles Qi, Sr. Design Engineering Architect, and Neil Robinson, Product Marketing Director, IP Group, Cadence Today’s cars are a full-fledged electronic system on wheels, where every part is interrelated and must be designed, optimized, and verified simultaneously. As a result, it’s important to apply a holistic approach when developing automotive systems, taking into consideration t... » read more

Blog Review: Jan. 16
By Jesse Allen - 16 Jan, 2019 - Comments: 0

Mentor's Harry Foster takes a look at how quickly FPGAs are adopting recent verification techniques, with formal gaining at a rapid pace. Cadence's Paul McLellan checks out the details of two new RISC-V based cores: Western Digital's open source SweRV and Esperanto's Maxion. Synopsys' Taylor Armerding digs into a recent cybersecurity report from the U.S. government and finds a troubling n... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Jan, 2019 - Comments: 0

M&A QuickLogic acquired SensiML Corporation. Founded in 2017 as a spin-off from Intel, SensiML provides a Software-as-a-Service suite for developing pattern matching sensor algorithms optimized for ultra-low power consumption using machine learning. Details of the deal were not disclosed, though QuickLogic will fund it with shares of common stock. IP CEVA debuted an all-purpose, hybrid... » read more

IoT Merging Into Data-Driven Design
By Ed Sperling and Kevin Fogarty - 10 Jan, 2019 - Comments: 0

The Internet of Things is becoming more difficult to define and utilize for an effective business strategy. While an increasing number devices send data to the cloud or some local server, so much data is being generated and moved around that new strategies are being developed to rethink what needs to be processed where. Back in 2013, when the IoT concept really began taking off, connectivity... » read more

Mixed-Signal Methodology Guide
By Cliosoft - 09 Jan, 2019 - Comments: 0

ClioSoft wrote the chapter on SoC design data management in Cadence’s "Mixed-Signal Methodology Guide." Register to receive an electronic copy of this chapter. Introduction Software teams have long used version control and data management systems and they have become an integral part of a software development environment. Practically, no significant software project is started without a so... » read more

Blog Review: Jan. 9
By Jesse Allen - 09 Jan, 2019 - Comments: 0

Cadence's Paul McLellan considers the challenges facing copper interconnects as resistance gets harder to deal with and the pros and cons of potential replacement materials. Mentor's Harry Foster digs into how FPGA design and verification engineers spend their time, and why the time designers spend designing has increased. Synopsys' Taylor Armerding contends that the way we use passwords ... » read more

Consolidating RF Flow for High-Frequency Product Design
By Cadence - 09 Jan, 2019 - Comments: 0

Design flows are currently fragmented due to the use of poorly connected EDA tools for various design tasks. Fragmented flows are unable to meet new challenges such as increased system and circuit complexity, stricter bandwidth requirements, smaller device sizes, and changing packaging needs. In this white paper, we look at how the Cadence Virtuoso RF Solution provides a single, well-integrated... » read more

Blog Review: Jan. 2
By Jesse Allen - 02 Jan, 2019 - Comments: 0

Cadence's Paul McLellan listens in as Uhnder CEO Manju Hegde explains the most critical issues impacting sensor development for autonomous vehicles and why new radar systems are needed to fill in the gaps. Synopsys' Fred Bals shares key points from the U.S. House Oversight and Government Reform Committee's investigation into the massive Equifax data breach that show how relatively small secu... » read more

Making IP Friendlier
By Brian Bailey - 27 Dec, 2018 - Comments: 2

Semiconductor Engineering sat down to discuss IP tracking and management with Ranjit Adhikary, vice president of marketing for ClioSoft; Jim Bruister, director digital systems (since retired) at Silvaco; Marc Greenberg, product marketing group director at Cadence; and Kelvin Low, vice president of marketing at Arm. What follows are excerpts from that conversation. Part one can be found here. ... » read more

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