tag: Cadence

Dealing With Deadlocks
By Ann Mutschler - 26 Oct, 2017 - Comments: 1

Deadlocks are becoming increasingly problematic as designs becoming more complex and heterogeneous. Rather than just integrating IP, the challenge is understanding all of the possible interactions and dependencies. That affects the choice of IP, how it is implemented in a design, and how it is verified. And it adds a whole bunch of unknowns into an already complex formula for return on inves... » read more

Use Model Versatility: Key To Return On Investment For Emulation
By Frank Schirrmeister - 26 Oct, 2017 - Comments: 0

When we announced Palladium Z1 now almost two years ago in November 2015, we emphasized versatility of use models as a key component to optimize return on investment when adopting emulation. Today, our biggest customers are using emulation as a compute resource with 10s of projects in parallel, and they are running a large number of different use models on it. This year alone, more than 30 cust... » read more

Blog Review: Oct. 25
By Jesse Allen - 25 Oct, 2017 - Comments: 0

Mentor's Joe Hupcey III explains the benefits of prioritizing faults with formal analysis before launching detailed fault verification. Cadence's Paul McLellan listens in as AMD's Mark Papermaster discusses what's needed to keep driving Moore's Law. Synopsys' Jesse Victors takes a look at ROCA, the latest flaw affecting RSA cryptography, and argues it may be time for a new encryption sche... » read more

The Week In Review: Design
By Jesse Allen - 20 Oct, 2017 - Comments: 0

M&A Synopsys acquired Sidense, a provider of antifuse one-time programmable (OTP) non-volatile memory (NVM) for standard-logic CMOS processes. Sidense was founded in 2004 in Canada. Terms of the deal were not disclosed. ArterisIP acquired the software and intellectual property rights of iNoCs, a provider of network-on-chip IP and design tools. Founded in 2007, the Swiss company was spun... » read more

Blog Review: Oct. 18
By Jesse Allen - 18 Oct, 2017 - Comments: 0

Mentor's Nitin Bhagwath suggests some ways to deal with undesirable signal integrity effects in DDR designs. Cadence's Ken Willis argues that for multi-gigabit serial link interfaces, signal integrity analysis should start upstream of the traditional post-layout verification step. Synopsys' Ravindra Aneja contends that understanding formal core data can reduce the overall effort and short... » read more

New Power Concerns At 10/7nm
By Ann Mutschler - 16 Oct, 2017 - Comments: 1

As chip sizes and complexity continues to grow exponentially at 7nm and below, managing power is becoming much more difficult. There are a number of factors that come into play at advanced nodes, including more and different types of processors, more chip-package decisions, and more susceptibility to noise of all sorts due to thinner insulation layers and wires. The result is that engineers ... » read more

The Week In Review: Design
By Jesse Allen - 13 Oct, 2017 - Comments: 0

Storage Western Digital uncorked disk drives based upon microwave-assisted magnetic recording technology. MAMR technology is one of two energy-assisted technologies the company has under development, the other being heat-assisted magnetic recording. Of the two, Western Digital said only MAMR has achieved the reliability required in data centers. The company noted that densities of its MAMR dev... » read more

High Performance, Low Power, And Test: DFT’s Impact On System PPA And Safety
By Rob Knoth - 12 Oct, 2017 - Comments: 0

Back in the day, test was an afterthought in system design and implementation. It was a separate task that could be added to the end of a project schedule—essentially, a checkbox before sending a design for manufacture or during product qualification. Nowadays, test is no longer an afterthought, and we’ll see it continue to grow in importance. Safety-critical semiconductor applications h... » read more

Data Centers Turn To New Memories
By Ann Mutschler - 12 Oct, 2017 - Comments: 3

DRAM extensions and alternatives are starting to show up inside of data centers as the volume of data being processed, stored and accessed continues to skyrocket. This is having a big impact on the architecture of data centers, where the goal now is to move processing much closer to the data and to reduce latency everywhere. Memory has always been a key piece of the Von Neumann compute archi... » read more

Trimming Waste In Chips
By Brian Bailey - 12 Oct, 2017 - Comments: 0

Extra circuitry costs money, reduces performance and increases power consumption. But how much can really be trimmed? When people are asked that question they either get defensive or they see it as an opportunity to show the advantages of their architecture, design process or IP. The same holds true for IP suppliers. Others point out that the whole concept of waste is somewhat strange, becau... » read more

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