tag: Cadence

Blog Review: April 1
By Jesse Allen - 01 Apr, 2026 - Comments: 0

Siemens EDA's Harry Foster considers why first-silicon success is continuing to decline even though tools are capable of handling much larger design sizes and identifies how increasingly complex interactions between components cause traditional verification assumptions to break down. Synopsys' Eldo N Baby explores dynamic voltage drop analysis, including how to bring in switching scenario in... » read more

Memory Wall Gets Higher
By Brian Bailey - 26 Mar, 2026 - Comments: 1

Key Takeaways An increasing percentage of the chip area is consumed by the same amount of SRAM for each node shrink. The problem is not limited to leading-edge AI, as it will eventually impact even small MCUs and MPUs. Architectural changes may be required. Stacking SRAM chiplets on logic is possible but expensive. SRAM is a vital piece of all computing systems, but its fail... » read more

Shift Verification Left: AI Tools For Faster, Smarter Chip Design
By Hamid Shojaei - 26 Mar, 2026 - Comments: 0

Verification activities can consume up to 70% of an overall chip project's effort, underscoring the central challenge that verification poses in today's semiconductor development (Cadence SoC Verification report). The most time-consuming activities, debugging and coverage closure, require significant coordination between design and verification teams and largely dictate overall time-to-ma... » read more

Data Boom Puts Pressure On NoCs, Fabrics
By Liz Allan - 26 Mar, 2026 - Comments: 0

Key Takeaways: NoC challenges, such as wiring congestion, timing closure, and performance, must be considered in tandem with topology and placement. Topologies can be customized to meet an application’s specific data flow needs, with a system containing multiple topologies to suit different data or zones. What is challenging for one type of system, such as an SoC, switch, or AI chi... » read more

Blog Review: Mar. 25
By Jesse Allen - 25 Mar, 2026 - Comments: 0

Synopsys' Jayraj Nair checks out how a model-based systems engineering workflow can help manage the complex multiphysics analysis needed to optimize heterogeneous systems. Siemens' Melville Bryant explains the difference between semiconductor traceability and tracking and why they're both essential, especially for complex multi-die devices. Cadence's Jamdagni Trivedi checks out VIP option... » read more

Auto Ethernet 10BASE-T1S Steps Up, With Tbps On The Horizon
By Liz Allan - 23 Mar, 2026 - Comments: 0

Key Takeaways: Automotive Ethernet, particularly 10BASE-T1S, is emerging as a replacement for CAN in vehicle networks, with higher speeds anticipated for future autonomous and connected cars. The transition to Ethernet in automotive domains is not universal; some OEMs may retain CAN or LIN in certain areas due to cost, and integrating various Ethernet standards can be technically feasib... » read more

Chip Industry Week In Review
By The SE Staff - 20 Mar, 2026 - Comments: 0

War impacts The Iran War's toll on the chip industry is widening. Over 95% of Taiwan's energy is imported, causing the country to secure alternative sources. Korea is also heavily dependent on energy imports from the Middle East. Shortages of key materials are cropping up everywhere. Helium from Qatar, the second largest producer behind the U.S., is constrained by hostilities in the Per... » read more

Advanced Packaging Limits Come Into Focus
By Gregory Haley - 19 Mar, 2026 - Comments: 0

Key Takeaways: Packaging is now a performance variable. Substrate, bonding, and process sequence determine what can be built at scale. Warpage underlies most advanced packaging failures and gets harder to control as package sizes grow. Every proposed solution, such as glass, panel processing, and backside power, solves one problem while creating another. Moore's Law has shif... » read more

Blog Review: Mar. 18
By Jesse Allen - 18 Mar, 2026 - Comments: 0

Cadence's Jamdagni Trivedi explains the UALink Protocol Level Interface, which defines how devices exchange data and control information, and shares insights into its structure, functionality, and significance in multi-node accelerator systems. Synopsys' Dustin Todd argues that AI sovereignty will be defined by and built on strategic interdependence, where countries develop and retain meanin... » read more

CPO Is Extending The Limits Of What’s Possible In AI Data Centers
By Ann Mutschler - 12 Mar, 2026 - Comments: 0

Key Takeaways I/O architecture must be co-designed with compute from day one. Partitioning SoCs into heterogeneous chiplets (compute, EIC, PIC, lasers) directly affects power delivery, floor-planning, interconnect topology, and system scalability. Successful CPO designs require architects to think in multi-physics terms, balancing electrical signaling, thermal stability, optical beha... » read more

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