tag: deposition

Ruthenium Liners Give Way To Ruthenium Lines
By Katherine Derbyshire - 17 Aug, 2017 - Comments: 0

For several years now, integrated circuit manufacturers have been investigating alternative barrier layer materials for copper interconnects. As interconnect dimensions shrink, the barrier accounts for an increasing fraction of the total line volume. As previously reported, both cobalt and ruthenium have drawn substantial interest because they can serve as both barrier and seed layers, minimizi... » read more

Is 7nm The Last Major Node?
By Ed Sperling - 20 Jul, 2017 - Comments: 3

A growing number of design and manufacturing issues are prompting questions about what scaling will really look like beyond 10/7nm, how many companies will be involved, and which markets they will address. At the very least, node migrations will go horizontally before proceeding numerically. There are expected to be more significant improvements at 7nm than at any previous node, so rather th... » read more

New BEOL/MOL Breakthroughs?
By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

Electroplating IC Packages
By Mark LaPedus - 10 Apr, 2017 - Comments: 2

The electrochemical deposition (ECD) equipment market for IC packaging is heating up as 2.5D, 3D and fan-out technologies begin to ramp. [getentity id="22817" e_name="Applied Materials"]  recently rolled out an ECD system for IC packaging. In addition, Lam Research, TEL and others compete in the growing but competitive ECD equipment market for packaging. ECD—sometimes referred to as pl... » read more

Following Multiple Patterns
By Mark LaPedus - 16 Mar, 2017 - Comments: 2

The lithography market is in flux. Today, chipmakers plan to extend today’s 193nm immersion lithography and multi-patterning to at least 10nm and 7nm. For the most critical layers, though, it’s unclear if optical lithography can extend beyond 7nm. For that reason, chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm. To get a handle on the state of patterning, S... » read more

TFETs Cut Sub-Threshold Swing
By Katherine Derbyshire - 16 Mar, 2017 - Comments: 0

One of the main obstacles to continued transistor scaling is power consumption. As gate length decreases, the sub-threshold swing (SS) — the gate voltage required to change the drain current by one order of magnitude — increases. As Qin Zhang, Wei Zhao, and Alan Seabaugh of Notre Dame explained in 2006, SS faces a theoretical minimum of 60 mV/decade at room temperature in conventional MO... » read more

Inside Advanced Patterning
By Mark LaPedus - 15 Dec, 2016 - Comments: 0

Prabu Raja, group vice president and general manager for the Patterning and Packaging Group at [getentity id="22817" e_name="Applied Materials"], sat down with Semiconductor Engineering to discuss the trends in patterning, selective processes and other topics. Raja is also a fellow at Applied Materials. What follows are excerpts of that conversion. SE: From your standpoint, what are the big... » read more

Timing Closure Issues Resurface
By Ed Sperling - 07 Dec, 2016 - Comments: 1

Timing closure has resurfaced as a major challenge at 10nm and 7nm due to more features and power modes, increased process variation and other manufacturing-related issues. While timing-related problems are roughly correlated to rising complexity in semiconductors, they tend to generate problems in waves—about once per decade. In SoCs, timing closure problems have spawned entire methodolog... » read more

200mm Equipment Shortfall
By Mark LaPedus - 21 Jul, 2016 - Comments: 0

A surge in demand for consumer electronics, communications ICs, sensors and other products has created a shortage in 200mm fab capacity that shows no signs of abating. None of these chips need to be manufactured using the most advanced processes, and there have been enough tweaks to processes at established nodes to eke even more out of existing processes. But that has left chipmakers strugg... » read more

Back-End-of-Line (BEOL) Metallization
By Coventor - 22 Jun, 2016 - Comments: 0

Physical Vapor Deposition (PVD) for Back-End-of-Line (BEOL) metallization is being pushed to the limits at the 16-nanometer (nm) technology node and beyond. Extending PVD for metal liner and barrier seed deposition is forcing the process into a narrow window that must be characterized prior to manufacturing introduction. Furthermore, understanding the liner dependency on the trench and via etch... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy