tag: finFETs

Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Performance
By Yu De Chen - 21 Oct, 2021 - Comments: 0

Profile variation is one of the most important problems during semiconductor device manufacturing and scaling. These variations can degrade both chip yield and device performance.  Virtual fabrication can be used to study profile variation in a very effective and economical manner and avoid process cycle time and wafer cost in the fab. In this short article, we will review the impact of STI (s... » read more

Building Complex Chips That Last Longer
By Ed Sperling - 23 Sep, 2021 - Comments: 0

Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Angstrom-Level Measurements With AFMs
By Mark LaPedus - 19 Aug, 2021 - Comments: 0

Competition is heating up in the atomic force microscopy (AFM) market, where several vendors are shipping new AFM systems that address various metrology challenges in packaging, semiconductors and other fields. AFM, a small but growing field that has been under the radar, involves a standalone system that provides surface measurements on structures down to the angstrom level. (1 angstrom = 0... » read more

Impact Of GAA Transistors At 3/2nm
By Brian Bailey - 16 Aug, 2021 - Comments: 2

The chip industry is poised for another change in transistor structure as gate-all-around (GAA) FETs replace finFETs at 3nm and below, creating a new set of challenges for design teams that will need to be fully understood and addressed. GAA FETs are considered an evolutionary step from finFETs, but the impact on design flows and tools is still expected to be significant. GAA FETs will offer... » read more

Using A Virtual DOE To Predict Process Windows And Device Performance Of Advanced FinFET Technology
By Qingpeng Wang - 03 Aug, 2021 - Comments: 0

By Qingpeng Wang, Yu De Chen, Cheng Li, Rui Bao, Jacky Huang, and Joseph Ervin Introduction With continuing finFET device process scaling, micro loading control becomes increasingly important due to its significant impact on yield and device performance [1-2]. Micro-loading occurs when the local etch rate on a wafer is dependent upon existing feature sizes and local pattern density. Uninten... » read more

Designing Chips In A ‘Lawless’ Industry
By Ed Sperling - 02 Aug, 2021 - Comments: 2

The guideposts for designing chips are disappearing or becoming less relevant. While engineers today have many more options for customizing a design, they have little direction about what works best for specific applications or what the return on investment will be for those efforts. For chip architects, this is proving to be an embarrassment of riches. However, that design freedom comes wit... » read more

Lower Power Chips: What To Watch Out For
By Ann Mutschler - 08 Jul, 2021 - Comments: 0

Low-power design in advanced nodes and advanced packaging is becoming a multi-faceted, multi-disciplinary challenge, where a long list of issues need to be solved both individually and in the context of other issues. With each new leading-edge process node, and with increasingly dense packaging, the potential for problematic interactions is growing. That, in turn, can lead to poor yield, cos... » read more

Thinner Channels With 2D Semiconductors
By Katherine Derbyshire - 21 Jun, 2021 - Comments: 0

Moving to future nodes will require more than just smaller features. At 3/2nm and beyond, new materials are likely to be added, but which ones and exactly when will depend upon an explosion of material science research underway at universities and companies around the globe. With field-effect transistors, a voltage applied to the gate creates an electric field in the channel, bending the ban... » read more

Power Optimization: What’s Next?
By Brian Bailey - 17 May, 2021 - Comments: 2

Concerns about the power consumed by semiconductors has been on the rise for the past couple of decades, but what can we expect to see coming in terms of analysis and automation from EDA companies, and is the industry ready to make the investment? Ever since Dennard scaling stopped providing automatic power gains by going to a smaller geometry, circa 2006, semiconductors have been increasing... » read more

The Future Of FinFETs At 5nm And Beyond
By Assawer Soussou - 05 Mar, 2021 - Comments: 0

While contact gate pitch (GP) and fin pitch (FP) scaling continues to provide higher performance and lower power to finFET platforms, controlling RC parasitics and achieving higher transistor performance at technology nodes of 5nm and beyond becomes challenging. In collaboration with Imec, we recently used SEMulator3D virtual fabrication to explore an end-to-end solution to better underst... » read more

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