tag: FPGAs

Will 10nm Be The Last Big Node?
By Ed Sperling - 19 Feb, 2015 - Comments: 0

There is a great deal of attention being paid to established nodes these days and everything up to and including 10nm. What comes after that remains a mystery. Intel and a handful of others will keep pushing to the next nodes, of course. Still, where the commercial foundries—including Intel—place their next big bets is a matter of ongoing debate. There is no doubt that 7nm and 5nm will b... » read more

Plunify: FPGA Design Closure
By Ed Sperling - 09 Feb, 2015 - Comments: 0

The number of EDA startups has plummeted around the globe, and nowhere is this more evident than in Singapore. In fact, there is exactly one EDA startup in that country—[getentity id="22672" e_name="Plunify"]—and even that isn't so new. Plunify started life in 2009 as a cloud-based startup, whose mission was to provide public cloud compute services to companies developing FPGAs. While th... » read more

Low Power Everything
By Ed Sperling - 15 Jan, 2015 - Comments: 0

A decade ago, former International Rectifier CEO Alex Lidow pronounced that there were three main categories for saving energy on a mass scale—variable speed motors, fluorescent lighting, and more efficient servers. He was right at the time. Those weren't necessarily semiconductor-driven markets, but they were the place where the most power could be saved. In fact, at the time, the rough e... » read more

What Will Change In Design For 2015?
By Brian Bailey - 15 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

FPGA Verification with Assertions: Why Bother?
By Mentor, a Siemens Business - 17 Dec, 2014 - Comments: 0

This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting simulation debugging time in half, as well as finding very complex bugs that are likely to escape traditional simulation without assertions. To read more, click here. » read more

Hybrid Verification: The Only Way Forward
By Brian Bailey - 20 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="10" kc_name=" functional verification"]. The inability of RTL [getkc id="11" kc_name="simulation"] to keep up with verification needs is causing rapid change in the industry. Taking part in the discussion are Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Janick Bergeron, fe... » read more

Blog Review: Nov. 5
By Ed Sperling - 05 Nov, 2014 - Comments: 0

Cadence's Brian Fuller zeroes in on ISO 26262, the automotive safety standard that's supposed to guard against nightmare failures in your car. Hopefully it works. They won't protect against cyber terrorism, though. Rambus' Aharon Etengoff takes a look at the challenges of connected vehicles. Mentor's J. Van Domelen looks at NASA's increased reliance on commercial partners, which has not b... » read more

High Throughput GSPS Signal Processing For FPGAs And ASICs Using Synthesizable IP Cores
By Synopsys - 24 Sep, 2014 - Comments: 0

This whitepaper illustrates how parallel processing synthesizable [getkc id="43" comment="IP"] cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or r... » read more

New Winners And Losers
By Brian Bailey - 24 Jul, 2014 - Comments: 0

During DAC 2013, Robert Colwell of DARPA said he was attempting to prepare the U.S. Dept. of Defense for what he believes is the cataclysm caused by the end of [getkc id="74" comment="Moore's Law"]. He asked the question, “What happens when we don’t have a new technology that doubles the number of transistors every couple of years?” Colwell believes that power is the primary reason why... » read more

Productive Clock Domain Crossing Verification
By Kiran Vittal - 08 May, 2014 - Comments: 2

Recently, we were invited to participate in an internal Chips@Cisco event along with other EDA vendors and FPGA providers. Executives from these vendors participated in a panel to discuss the challenges seen by the technology leaders in FPGAs and what it means to the industry. Everyone on the panel agreed that design size and complexity, including clock domains, is continuing to follow Moore’... » read more

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