tag: IP integration

IP Market Booms At Advanced Nodes
By Ann Mutschler - 26 Feb, 2015 - Comments: 0

As [getkc id="81" kc_name="SoC"] design and manufacturing costs rise, system OEMs are wringing as much of that increase as they can from ASIC vendors. The result is that engineering teams on the design and test side are being constrained by budgets at a time when complexity is rising and time-to-market pressures are increasing. At least one segment is benefiting from directly this. Budgetary... » read more

Enabling The Next Mobile Computing Revolution
By Brian Jeff - 07 Aug, 2014 - Comments: 0

We’ve come a long way Just think about the ‘mobile computing’ revolution over the last five years – the compute tasks we routinely handle on our mobile phonesdaily, equal those that were only possible to execute using laptops and desktops several years ago. With a direct and uninterrupted power supply from the wall, laptopsand desktops require fan-assisted cooling, a... » read more

Distortion Effects Prevail In RF Design
By Ann Mutschler - 27 Mar, 2014 - Comments: 0

It’s an exciting time for consumers of wireless devices, but it’s a challenging time for system designers who must design, analyze and verify that all of the components in those wireless devices interoperate. In wireless designs, distortion effects play an important role in the performance of RF circuits, including mixers, low-noise amplifiers (LNAs) and power amplifiers (PAs) and managi... » read more

Experts At The Table: Next-Generation IP Landscape
By Ann Mutschler - 22 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

The Rise Of Layout-Dependent Effects
By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Designing for today’s advanced semiconductor manufacturing process nodes brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Layout-dependent effects (LDE), which emerged at 40nm and are having a larger impact at 28 and 20nm, introduce variability to circuit ... » read more

SoC Architects Face Big Challenges
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler While the geometries of advanced node processes such as 28nm and below may not greatly impact SoC architectures, the complexity enabled by the leading edge brings intense challenges all the same. With the ability to put more transistors onto a chip come new possibilities such as the increasing use of multi-core architectures and lots of integrated hardware en... » read more

Power Impacts On Advanced Node IP
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ann Steffora Mutschler With the move to the 28nm or 20nm process nodes, SoC engineering teams are seeing a significant amount of variations due to manufacturability. To reflect how a design element will be printed on the wafer, foundries offer many libraries with multiple corners for different voltages, timing and temperature, among other things. “At 28nm what we are seeing is a l... » read more

Experts at the Table: Black Belt Power Management
By Ann Mutschler - 11 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Low-Power/High-Performance Engineering sat down to discuss rising integration challenges caused by an increasing amount of black-box IP with Qi Wang, technical marketing group director, solutions marketing, for the low-power and mixed-signal group at Cadence; J. Bhasker, architect at eSilicon Corp.; Navraj Nandra, senior director of product marketing for analog an... » read more

Reducing Circuitry To Reduce Power
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler Power is at the top of the list of concerns for design teams today. Consequently, engineers are constantly looking at new techniques and architectural approaches to lower and management the power and energy consumption of their devices. This has resulted in some incredible engineering feats, turning parts of a device on and off as needed, applying different volta... » read more

Experts At The Table: Black Belt Power Management
By Ann Mutschler - 14 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler With approximately 80% of SoC content reused from past designs or brought in from internal and external IP sources, a significant part of a design engineer’s job today is writing glue logic and verifying to make sure the integrated system communicates as dictated by the specification. Integration challenges continue to mount with the increasing amount of black ... » read more

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