Chip Industry Week in Review


SEMICON West was held in Phoenix this week, with presentations covering heterogeneous integration, AI, quantum, supply chain resilience, and more. Amid the buzz of the conference, some key manufacturing and test announcements were made this week: The strategic importance of the Phoenix area hub was highlighted. Amkor Technology broke ground this week on its advanced packaging and test camp... » read more

Location Verification Becomes Much Bigger Concern For Chips


Location verification is gaining traction as a way of strengthening supply chain oversight with minimal effort, fueled by tightening export controls and growing concerns about AI chip smuggling and counterfeiting. In the past, this kind of tracking was done by having one or more employees literally watch over a production run at a fab, follow the chips all the way to their destination, and a... » read more

How The Cyber Resilience Act Shifts Open-Source Responsibility To Vendors


The EU Cyber Resilience Act (CRA), adopted last year, aims to strengthen product security in several ways. One of its most ambitious goals is the elimination of exploitable vulnerabilities from digital products. Vendors are now obligated to identify vulnerabilities, resolve them before delivery, and continue addressing them throughout the product’s lifecycle. The scale of the challenge The ... » read more

New Approaches To Limit Cyberattacks On Hardware


The number and value of cyberattacks on semiconductors is rising, but new approaches to designing and packaging chips could put a significant dent in those figures. Semiconductor-related cybersecurity attacks have multiplied more than six times since 2022, according to a report by cyber intelligence firm CloudSEK. These attacks have cost the semiconductor industry an estimated $1.05 billion ... » read more

Blog Review: Oct. 8


Siemens' Azat Latypov presents a stochastic-aware optical proximity correction strategy that demonstrated an order-of-magnitude reduction in the probability of stochastic defects for both SRAM and logic designs, sacrificing minor edge placement error in return for much lower failure rates. Cadence's Dimitry Pavlovsky introduces the AMBA CHI Chip-to-Chip (C2C) protocol, which extends the CHI ... » read more

How 3D-IC Will Change Chip Design


Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC design challenges and the impact on stacked die on EDA tools and methodologies, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities busine... » read more

Why The Next Breakthrough In Chips Depends On Rethinking Design Workflows


At this year’s DAC Chips to Systems Conference (DAC 2025), Keysight and its partners showcased how engineers are rethinking design workflows from chips to complete systems. The Partner Theater, hosted by Keysight brought together innovators from across the semiconductor ecosystem – each tackling one of today’s most pressing challenges: how to manage exploding volumes of design data and le... » read more

Chip Industry Week in Review


Samsung and SK hynix joined OpenAI's Stargate initiative to ensure there will be enough memory chips to meet the needs of AI data centers. The goal is to produce up to 900,000 DRAM wafer starts per month. OpenAI also inked agreements to explore the development of next-gen data centers in Korea. Axcelis Technologies (ion implantation systems) will merge with Veeco Instruments (compound semic... » read more

Blog Review: Oct. 1


Synopsys' Chun-Soo Kim and Hoseong Kim suggest making the entire design flow local layout effect-aware to identify and address issues early and ultimately improve PPA by avoiding overly pessimistic designs. Siemens' Kirk Fabbri explores the power distribution network, focusing on power plane capacitance and how it varies with the dynamic switching characteristics of the load and dielectric c... » read more

How To Cool 3D-ICs


Experts at the Table: Semiconductor Engineering sat down to discuss how to cool 3D-ICs and what's missing from the tool chain today, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager at Keysigh... » read more

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