Virtual Process Game To Benchmark Performance of Humans And Computers For Design Of A Semiconductor Fabrication Process


A new technical paper titled "Human–machine collaboration for improving semiconductor process development" was published by researchers at Lam Research. Abstract: "One of the bottlenecks to building semiconductor chips is the increasing cost required to develop chemical plasma processes that form the transistors and memory storage cells These processes are still developed manually using h... » read more

Blog Review: March 1


Siemens EDA's Chris Spear explains the UVM Factory and how it can facilitate collaboration by enabling injection of new features without affecting your team. Cadence's Paul McLellan looks at efforts to ensure chiplets from different companies work together, particularly when the creating companies didn't pre-plan for those specific chiplets to work together, as well as the problems of failur... » read more

Week In Review: Semiconductor Manufacturing & Test


The Biden Administration’s export bans for semiconductor manufacturing equipment are delaying expansion plans for Chinese chipmakers, Nikkei Asia reports. Yangtze Memory Technologies (YMTC) has halted work on its second memory plant near Wuhan, and ChangXin Memory Technologies (CMTX) says its second production facility, slated to open in 2023, will be delayed until 2024 or 2025. In an effo... » read more

Devices And Transistors For The Next 75 Years


The 75th anniversary of the invention of the transistor sparked a lively panel discussion at IEDM, spurring debate about the future of CMOS, the role of III-V and 2D materials in future transistors, and what will be the next great memory architecture.[1] Industry veterans from the memory, logic, and research communities see high-NA EUV production, NAND flash with 1,000 layers, and hybrid bon... » read more

The Other Side Of The Wafer: The Latest Developments In Backside Power Delivery


At the beginning of my career in semiconductor equipment, the backside of the wafer was a source of anxiety. In one memorable instance in my early career, several wafers flew off a robot blade during a wafer transfer. After cleaning up the mess, we remembered that a variety of thin films could be deposited on the wafer backside, which could decrease its friction coefficient. Slowing down the wa... » read more

Blog Review: Feb. 8


Cadence's Sanjeet Kumar points to key changes and optimizations that are done for USB3 Gen T compared to USB3 Gen X tunneling in order to minimize tunnel overhead and maximize USB3 throughput. Siemens EDA's Harry Foster considers the effectiveness of IC and ASIC verification by looking at schedule overruns, number of required spins, and classification of functional bugs. Synopsys' Chris C... » read more

Big Changes Ahead For Chip Technology And Industry Dynamics


Semiconductor Engineering sat down to discuss the impact of customization and advanced packaging, and concerns about reliability and geopolitical rivalries with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computational products at Lam Research; and Ankur Gupta, vice president and general manager of the test group and lifecycle s... » read more

Chip Industry’s Earnings Roundup


Editor's Note: Updated throughout February 2023 for additional earnings releases. Many companies reported revenue growth in the most recent quarter, but the latest round of chip industry earnings releases reflected some major themes: Demand for consumer electronics softened due to inflation, rising interest rates, and post-pandemic market saturation, creating a slump in the memory chip ... » read more

Collaboration Widens Among Big Chip Companies


Experts at the Table: Semiconductor Engineering sat down to discuss the growing need for collaboration among equipment and tools vendors, the impact of systems companies and increases in complexity, and how to handle a push for more customization while controlling costs, with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computati... » read more

Blog Review: Jan. 18


Synopsys' Dana Neustadter, Sara Zafar Jafarzadeh, and Ruud Derwig argue that we are already at an inflection point for post-quantum security because devices and infrastructure systems with longer life cycles or communicating data that must be kept confidential for an extended period need to have a path towards quantum-safe solutions. Siemens EDA's Harry Foster looks at trends in adoption of ... » read more

← Older posts Newer posts →