Identifying DRAM Failures Caused By Leakage Current And Parasitic Capacitance


Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability issues, even when there are no obvious structural abnormalities in the underlying device. Leakage current has become a critically important component in DRAM device design. Fig. 1 (a) DRAM Memory Cell, (b) GI... » read more

Week In Review: Manufacturing, Test


Coronavirus The coronavirus in China has been declared as a global health emergency by the World Health Organization (WHO). The situation appears to be much worse than SARS (severe acute respiratory syndrome), which hit in 2003. Several companies are taking precautionary measures to prevent widespread transmission of coronavirus. For example, ASE has devoted a Web page for the measures it is t... » read more

Week In Review: Manufacturing, Test


Market research What are the hot chip markets for 2020? IC Insights released its rankings of sales growth rates for each of the 33 IC product categories defined by the World Semiconductor Trade Statistics (WSTS) organization. “After posting the two worst growth rates among all IC product categories in 2019, NAND flash and DRAM are forecast to be among the top three fastest-growing IC segment... » read more

SiC Foundry Business Emerges


Several third-party foundry vendors are entering or expanding their efforts in the silicon carbide (SiC) business amid booming demand for the technology. However, making a significant dent in the market will not be so easy for SiC foundry vendors and their customers. They are facing stiff competition from traditional SiC device vendors such as Cree, Infineon, Rohm and STMicroelectronics. ... » read more

5/3nm Wars Begin


Several foundries are ramping up their new 5nm processes in the market, but now customers must decide whether to design their next chips around the current transistor type or move to a different one at 3nm and beyond. The decision involves the move to extend today’s finFETs to 3nm, or to implement a new technology called gate-all-around FETs (GAA FETs) at 3nm or 2nm. An evolutionary step f... » read more

Speeding Up Process Optimization Using Virtual Fabrication


Author: Joseph Ervin Director, Semiconductor Process and Integration Lam Research Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patte... » read more

Week In Review: Manufacturing, Test


Chipmakers A fire broke out this week at a joint NAND flash fab between Western Digital (WD) and Kioxia. Kioxia is the former Toshiba NAND flash unit that was recently spun out by the Japanese company. “On Monday, January 6, (morning, January 7 local time) a small fire occurred at one of our joint venture facilities in Yokkaichi, Japan. Local firefighters quickly extinguished the fire, and w... » read more

Where Technology Breakthroughs Are Needed


After years of delays, extreme ultraviolet (EUV) lithography is finally in production at the 7nm logic node with 5nm in the works. EUV, a next-generation lithography technology, certainly will help chipmakers migrate to the next nodes. But EUV doesn’t solve every problem. Nor does it address all challenges in the semiconductor industry. Not by a long shot. To be sure, the industry needs... » read more

Week In Review: Manufacturing, Test


Fab tools and materials In a blog, David Haynes, managing director of strategic marketing at Lam Research, talks about the IoT and automotive chip markets, which are fabricated at a wide range of technology nodes. Hoya recently made an unsolicited $1.4 billion bid to acquire NuFlare, a supplier of e-beam mask writers and other equipment. Click here for more information. Hoya makes several p... » read more

An Introduction To Semiconductor Process Modeling


Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing. Unfortunately, developing a successful process can’t be done without some work. This blog will discuss an efficient technique to develop new process steps faster, with much less effort. Basic concept The easiest way to predict a process result is to model its b... » read more

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