tag: Lam Research

Searching For EUV Mask Defects
By Mark LaPedus - 19 Oct, 2017 - Comments: 2

Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this technology can be used in production. One lingering issue that is becoming more worrisome is how to find [gettech id="31045" comment="EUV"] mask defects. That isn't the only issue, of course. The industry continues to work on the power source and resists. Bu... » read more

MEMS Market Shifting
By Ed Sperling - 19 Oct, 2017 - Comments: 0

The MEMS sector is beginning to look more promising, bolstered by new end-market demand and different packaging options that require more advanced engineering, processes and new materials. All of this points to higher selling prices, which are long overdue in this space. For years, the market for microelectromechanical systems was populated by too many companies vying for too few opportunit... » read more

Controlling Uniformity At The Edge
By Aaron Eppler - 19 Oct, 2017 - Comments: 0

Chipmakers want every part of the wafer to produce, or yield, good die. Advances in process technologies over the years have just about made this a reality, even as feature dimensions continue to shrink and devices grow ever more complex. Now, the last frontier is improving yields at the edge of the wafer – the outer 10 mm or so – where chemical, physical, and even thermal discontinuitie... » read more

Reducing BEOL Parasitic Capacitance Using Air Gaps
By Michael Hargrove - 19 Oct, 2017 - Comments: 0

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology [1], and numerous schemes have been ... » read more

Next-Gen Mask Writer Race Begins
By Mark LaPedus - 19 Oct, 2017 - Comments: 5

Competition is heating up in the mask writer equipment business as two vendors—Intel/IMS and NuFlare—vie for position in the new and emerging multi-beam tool segment. Last year, Intel surprised the industry by acquiring IMS Nanofabrication, a multi-beam e-beam mask writer equipment vendor. Also last year, IMS, now part of Intel, began shipping the world’s first multi-beam mask writer f... » read more

Blog Review: Oct. 18
By Jesse Allen - 18 Oct, 2017 - Comments: 0

Mentor's Nitin Bhagwath suggests some ways to deal with undesirable signal integrity effects in DDR designs. Cadence's Ken Willis argues that for multi-gigabit serial link interfaces, signal integrity analysis should start upstream of the traditional post-layout verification step. Synopsys' Ravindra Aneja contends that understanding formal core data can reduce the overall effort and short... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 29 Sep, 2017 - Comments: 0

Chipmakers Who will buy Toshiba’s memory business? In the latest of what is becoming a confusing saga, Toshiba has signed a deal to sell its memory unit to a group led by Bain Capital. The Bain-led consortium will hold a 49.9% stake in the memory unit, while Toshiba will hold 40.2% and Japan’s Hoya will own 9.9%. Other members in the group include Apple, Dell, Kingston, and Seagate. In add... » read more

Blog Review: Sept. 27
By Jesse Allen - 27 Sep, 2017 - Comments: 0

Synopsys' Mukul Dawar highlights the biggest changes coming to the PCIe 4.0 specification, plus a peek at what's new in PCIe 5.0. Cadence's Paul McLellan considers why EDA startups are less common than they used to be. Mentor's David Abercrombie and Alex Pearson discuss new requirements for detecting double patterning errors at advanced nodes. Rambus' Aharon Etengoff reports that secur... » read more

Looming Issues And Tradeoffs For EUV
By Mark LaPedus - 25 Sep, 2017 - Comments: 5

Momentum is building for extreme ultraviolet (EUV) lithography, but there are still some major challenges to solve before this long-overdue technology can be used for mass production. [gettech id="31045" comment="EUV"] lithography—a next-generation technology that patterns tiny features on a chip—was supposed to move into production around 2012. But over the years, EUV has encountered se... » read more

Using Advanced Statistical Analysis To Improve FinFET Transistor Performance
By Jimmy Gu - 21 Sep, 2017 - Comments: 0

Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies. Due to the interaction of upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity) during actual fabrication, variations based upon process changes can be highly complex. Process simulators t... » read more

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