tag: lithography

Signoff Intensity On The Rise
By The SE Staff - 15 Aug, 2014 - Comments: 2

By Ann Steffora Mutschler and Ed Sperling Lithography and signoff are crossing swords at 16/14nm and 10nm, creating new problems that raise questions about just how confident design teams will be when they sign off before tapeout — and how many respins are likely to follow. While designs at 20nm, 16nm and 14nm typically rely on colorless double patterning, at 10nm colors are mandatory. ... » read more

DSA: Hype Or Revolution?
By Michael Watts - 14 Aug, 2014 - Comments: 0

Directed self-assembly (DSA) has become the subject of a great deal of research attention in the lithography world, to the point where there were dedicated sessions at this year’s Advanced Lithography conference in February. So is this just another passing research fad, or is it a technology that will revolutionize semiconductor manufacturing? DSA utilizes a block copolymer that effectivel... » read more

Why The Next Couple Process Nodes Are So Critical
By Ed Sperling - 14 Aug, 2014 - Comments: 0

In the greater scheme of things, one process node doesn't matter all that much. In fact, it has become common practice for big chipmakers to skip nodes for some of their chips as power issues becoming increasingly complex, time-to-market windows shrink and leapfrogging is viewed as a way to maximize resources while remaining über-competitive. But the next process node, and certainly the nex... » read more

Self-Aligned Double Patterning—Part Deux
By David Abercrombie - 14 Aug, 2014 - Comments: 0

In my last article, I introduced you to the basic Self-Aligned Double-Patterning (SADP) process that is one of the potential candidate techniques for processing metal layers at 10nm and below, but let’s have a quick recap. SADP uses a deposition and etch step process to create spacers surrounding a patterned shape (Figure 1). As you can see, there are two masking steps—the first mask is cal... » read more

EUV Is Key To 450mm Wafers
By Katherine Derbyshire - 31 Jul, 2014 - Comments: 1

Whether the wafers in question are 200 mm in diameter, or 300 mm, or potentially 450 mm, larger wafer sizes have always been justified by manufacturing economics. If the cost to process a wafer stays the same, but the wafer contains more devices, then the cost per device goes down. For processes that apply to the entire wafer at once — etch, deposition, cleaning, and so forth — the equation... » read more

EUV Light Source Makes Progress
By Kenji Tsuda - 30 Jul, 2014 - Comments: 0

EUV Lithography light source maker, Gigaphoton has developed a laser-produced plasma (LPP) light source prototype model that can produce a maximum of 92 watts. This is more than double the 43 watts produced using a traditional LPP light source. Figure 1 conceptual diagram of EUV exposure. Source: Gigaphoton/EUVA The biggest issue with EUV lithography has been the output power of the lig... » read more

IP Integration Challenges Rising
By Ann Mutschler - 24 Jul, 2014 - Comments: 0

It’s not just [getkc id="80" comment="lithography"] that is putting a crimp in sub-28nm designs. As more functions, features, transistors and software are added onto chips, the pressure to get chips out the door has forced chipmakers to lean more heavily on third-party IP providers. Results, as you might expect, have been mixed. The number of blocks has mushroomed, creating its own web of ... » read more

How Much Multipatterning?
By Ed Sperling - 19 Jun, 2014 - Comments: 2

The latest consensus among litho experts is that extreme ultraviolet (EUV) will appear in the market sometime in coming months in a commercially viable form. The only question is the degree of commercially viability, and what it will actually cost. While some debate lingers about whether EUV will ever get going, the general feeling is that enough progress has been made recently to make it work.... » read more

Manufacturing Bits: June 3
By Mark LaPedus - 03 Jun, 2014 - Comments: 0

World’s thinnest TFTs The U.S. Department of Energy’s Argonne National Laboratory has devised the world’s thinnest flexible, 2D thin-film transistors (TFTs). The transistors are just 10 atomic layers thick. TFTs are typically used in screens and displays. In the lab, Argonne researchers fabricated the TFTs on both a conventional silicon platform and a flexible substrate. [caption i... » read more

EDA Races To 7nm, Despite Litho Uncertainties
By Ann Mutschler - 16 May, 2014 - Comments: 0

It’s becoming almost painful to refer to the delay with EUV, but it certainly isn’t stopping anyone on the design side from tweaking design tools or working on test chips. Clearly, things are moving ahead to 7nm even though lithography plans aren't yet clear. Steve Carlson, group marketing director in Cadence’s Office of Chief Strategy, said with regard to EUV, “They have the power p... » read more

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