tag: Mentor

Blog Review: April 29
By Jesse Allen - 29 Apr, 2020 - Comments: 0

Arm's Paul Whatmough checks out SCALE-Sim, an open source cycle-accurate simulator specifically for neural processing unit (NPU) architectures. Mentor's Neil Johnson shows how a complete verification methodology requires complementary deployment of multiple techniques, with different options at each level of abstraction. Cadence's Paul McLellan checks out challenges in automotive reliabil... » read more

5G Brings New Verification Challenges
By Jean-Marie Brunet - 23 Apr, 2020 - Comments: 0

In the summer of 2018, Siemens raised a few eyebrows within the verification community when we acquired Sarokal, based in Finland. What that community did not piece together at the time was that Sarokal is the leader in 5G testing and has a seasoned team of people that have work closely with leading telecommunication companies to provide hardware and software solutions for fronthaul system test... » read more

Practical Processor Verification
By Brian Bailey - 23 Apr, 2020 - Comments: 0

Custom processors are making a resurgence, spurred on by the early success of the RISC-V ISA and the ecosystem that is rapidly building around it. But this shift is amid questions about whether processor verification has become a lost art. Years ago custom processors were common. But as the market consolidated around a handful of companies, so did the tools and expertise needed to develop th... » read more

Using Processor Trace At The System Level
By Ann Mutschler - 23 Apr, 2020 - Comments: 0

The race to process more data faster using less power is creating a series of debug challenges at the system level, where developers need to be able to trace interactions across multiple and often heterogeneous processing elements that may function independently of each other. In general, trace is a hardware debug feature that allows the run-time behavior of IP to be monitored. More specific... » read more

Porting Vivado HLS Designs To Catapult HLS Platform
By Mentor, a Siemens Business - 22 Apr, 2020 - Comments: 0

High-Level Synthesis (HLS) offers significant benefits when developing algorithms and intellectual property (IP) blocks for implementation in digital logic solutions such as Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASICs). FPGA vendors offer HLS tools and using those increases flexibility and productivity over traditional hardware description language ... » read more

Blog Review: April 22
By Jesse Allen - 22 Apr, 2020 - Comments: 0

Mentor's Shivani Joshi takes a look at the benefits of adding ground planes in PCB design to improve signal integrity and reduce electrical noise and interference. Cadence's Paul McLellan points to the gradual adoption of 3D packaged systems, the role of mobile in driving adoption, and the rise of chiplets. Synopsys' Taylor Armerding shares some tips for productive remote teamwork from th... » read more

Power Becomes Bigger Concern For Embedded Processors
By Ann Mutschler - 15 Apr, 2020 - Comments: 0

Power is emerging as the dominant concern for embedded processors even in applications where performance is billed as the top design criteria. This is happening regardless of the end application or the process node. In some high-performance applications, power density and thermal dissipation can limit how fast a processor can run. This is compounded by concerns about cyber and physical secur... » read more

Blog Review: April 15
By Jesse Allen - 15 Apr, 2020 - Comments: 0

Mentor's Neil Johnson argues that it's time to reevaluate the current definition of verification methodology, with a new focus on methodologies driven by the needs of the design and best suited to different abstractions. Synopsys' Derek Handova warns that the need to manage the security risks of billions of IoT devices will continue to change the requirements and scope of 5G security. Cad... » read more

Power Management And Integration Of IPs In SoCs: Part 1
By Progyna Khondkar - 09 Apr, 2020 - Comments: 0

IPs – whether in the form of soft or hard macros – are the epicenter of today’s SoC designs. Integration of IP with low power designs and conducting power aware (PA) verification are always complex and cumbersome. Because most of these IPs are self-contained, pre-verified at the block level, and must be preserved in their totality when integrated or verified at the SoC level. Until UPF... » read more

Designing Ultra Low Power AI Processors
By Ann Mutschler - 09 Apr, 2020 - Comments: 0

AI chip design is beginning to shift direction as more computing moves to the edge, adding a level of sophistication and functionality that typically was relegated to the cloud, but in a power envelope compatible with a battery. These changes leverage many existing tools, techniques and best practices for chip design. But they also are beginning to incorporate a variety of new approaches tha... » read more

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