tag: Mentor

Package Designers Need Assembly-Level LVS For HDAP Verification
By Mentor, a Siemens Business - 07 May, 2018 - Comments: 0

While advanced IC packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique package connectivity issues, such as missing or misplaced interposer/package bumps/pads, pin naming and text labeling issues, and the like, require new and enhanced LVS-like verification techniques that can move across the entire package to ensure proper connectivity and perfo... » read more

The Week In Review: Design
By Jesse Allen - 04 May, 2018 - Comments: 0

M&A ANSYS finalized its acquisition of OPTIS. Founded in 1989, OPTIS provided software for scientific simulation of light, human vision and physics-based visualization. The acquisition boosts the company's automotive simulation portfolio with radar, lidar and camera simulation. Terms were not disclosed. IP Arm debuted the Cortex-M35P processor. Aimed at IoT applications, the IP combine... » read more

The Coming Golden Age For Automotive E/E Design Services And Consulting
By Andrew Macleod - 03 May, 2018 - Comments: 0

By Andrew Macleod and Scott Majdecki The discipline of automotive E/E systems design is being transformed by trends like electrification and autonomous vehicles, which means there is a premium on methodologies like rapid platform (hardware/ software) prototyping, simulation and test, and electrical architecture optimization. Such methodologies hinge on advanced software design tools and the ... » read more

Engineering Challenges for Viable Autonomous Vehicles
By Mentor, a Siemens Business - 02 May, 2018 - Comments: 0

The rise of autonomous and electric vehicles brings with it a host of engineering implications, including an increase in the number and variety of sensors in the vehicle, increasing software and hardware complexity, massive validation and verification cycles, heightened safety and security requirements, and new demands for digital data continuity. This paper is an overview of how six interdisci... » read more

Blog Review: May 2
By Jesse Allen - 02 May, 2018 - Comments: 0

Arm's Greg Yeric looks towards the future of 3D ICs with a dive into transistor-level 3D, including the different proposed methods of stacking transistors, power/performance benefits, and challenges such as parasitic resistance. Mentor's Kurt Takara, Chris Kwok, Dominic Lucido, and Joe Hupcey III explain how a custom synchronizer methodology can help avoid CDC mistakes and errors in FPGA des... » read more

EDA In The Cloud (Part 2)
By Brian Bailey - 02 May, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the migration of EDA tools into the Cloud with Arvind Vel, director of product management at ANSYS; Michal Siwinski, vice president of product management at Cadence; Richard Paw, product marketing manager at DellEMC, Gordon Allan, product manager at Mentor, a Siemens Business; Doug Letcher, president and CEO of Metrics, Tom Anderson, technical marke... » read more

Partitioning Becomes More Difficult
By Ann Mutschler - 30 Apr, 2018 - Comments: 0

The divide-and-conquer approach that has been the backbone of verification for decades is becoming more difficult at advanced nodes. There are more interactions from different blocks and features, more power domains, more physical effects to track, and far more complex design rules to follow. This helps explain why the number of tools required on each design—simulation, prototyping, em... » read more

Interface DRC Can Streamline Chip-Level Interface Physical Verification
By James Paris - 26 Apr, 2018 - Comments: 0

In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the early floorplanning stages through tapeout. In early floorplanning stages, blocks placed in the chip-level floorplan are usually still under development. Merging these incomplete blocks with the... » read more

More Nodes, New Problems
By Ann Mutschler - 26 Apr, 2018 - Comments: 0

The rollout of leading-edge process nodes is accelerating rather than slowing down, defying predictions that device scaling would begin to subside due to rising costs and the increased difficulty of developing chips at those nodes. Costs are indeed rising. So are the number of design rules, which reflect skyrocketing complexity stemming from multiple patterning, more devices on a chip, and m... » read more

EDA In The Cloud
By Brian Bailey - 26 Apr, 2018 - Comments: 4

Semiconductor Engineering sat down to discuss the migration of EDA tools into the Cloud with Arvind Vel, director of product management at ANSYS; Michal Siwinski, vice president of product management at Cadence; Richard Paw, product marketing manager at DellEMC, Gordon Allan, product manager at Mentor, a Siemens Business; Doug Letcher, president and CEO of Metrics, Tom Anderson, technical marke... » read more

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