tag: Mentor

Choosing A Format For The Portable Stimulus Specification
By Mentor, a Siemens Business - 23 May, 2018 - Comments: 0

The Accellera Systems Initiative is currently defining a Portable Stimulus Specification (PSS) standard for verification models that can be used to generate appropriate tests for all levels and platforms automatically. The current draft of the standard includes two alternative input formats for these models. This paper examines the merits and challenges of both formats. To read more, click h... » read more

EDA In The Cloud (Part 3)
By Brian Bailey - 23 May, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss the migration of EDA tools into the Cloud with Arvind Vel, director of product management at ANSYS; Michal Siwinski, vice president of product management at Cadence; Richard Paw, product marketing manager at DellEMC, Gordon Allan, product manager at Mentor, a Siemens Business; Doug Letcher, president and CEO of Metrics, Tom Anderson, technical marke... » read more

Blog Review: May 23
By Jesse Allen - 23 May, 2018 - Comments: 0

Cadence's Paul McLellan digs into the problems of test for 3D ICs s well as new approaches to cell-aware test, modular test and realistic IR drop at CDNLive EMEA. Mentor's Colin Walls shares four more embedded software tips, including always initializing a variable and when to use ++i instead of i++. Synopsys' Taylor Armerding points to a new way that phishing attacks could get around Mic... » read more

The Power Of De-Integration
By Ed Sperling - 17 May, 2018 - Comments: 0

The idea that more functionality can be added into a single chip, or even into a single system, is falling out of vogue. For an increasing number of applications, it's no longer considered the best option for boosting performance or lowering power, and it costs too much. Hooman Moshar, vice president of engineering at Broadcom, said in a keynote speech at Mentor's User2User conference this w... » read more

Blog Review: May 16
By Jesse Allen - 16 May, 2018 - Comments: 0

Synopsys' Eric Huang looks back at why the USB On-The-Go specification was revolutionary in getting devices talking to each other and how the shift to USB Type-C and Dual Mode means it isn't needed anymore. Mentor's Andrew Macleod examines four different shift-left methodologies and the benefits of each in the context of automotive and autonomous vehicle design. Cadence's Paul McLellan ch... » read more

Optimizing Your DRC Debug Can Reap Big Productivity Gains
By Srinivas Velivala - 10 May, 2018 - Comments: 0

Debugging design violations found by design rule checking (DRC) has always taken a significant share of the time needed to get a design to tapeout. And debug time only increases as the number and complexity of DRC expands with each new process node. Any steps you can take to make your DRC debug process more efficient directly improves your productivity. One technique for minimizing debug tim... » read more

Power Optimization Strategies Widen
By Brian Bailey - 10 May, 2018 - Comments: 0

An increasing amount of electronic content in new and existing markets is creating different and sometimes competing demands for power optimization. For the past decade, EDA has been driven by the mobile phone industry, where the emphasis is on better power analysis and optimization tools to reduce power consumption and extend battery life. While energy efficiency continues to improve, other... » read more

Does Power Verification Work?
By Brian Bailey - 10 May, 2018 - Comments: 1

Functional verification continues to evolve, but power verification—a somewhat new concern—remains at levels of sophistication reminiscent of functional verification 30 years ago. When will power verification catch up and what must to happen to make it possible? These are questions that the industry is still grappling with, and not everyone believes they require answers. Functional error... » read more

Alchip Minimizes Dynamic Power For High-Performance Computing ASICs
By Mentor, a Siemens Business - 09 May, 2018 - Comments: 0

Alchip, a fabless ASIC provider, focuses on high-performance computing ASICs. They decided to undertake a new project where they would employ the PowerPro RTL Low-Power Platform to reduce dynamic power consumption within their unique fishbone clock tree methodology. Could they achieve better power results using PowerPro and could they integrate the tool within their team and the existing design... » read more

Blog Review: May 9
By Jesse Allen - 09 May, 2018 - Comments: 0

Mentor's Doug Amos explains the differences (and similarities) between verification and validation, why switching between engines needs to be simpler, and why the limits of verification are driving a growth in validation importance. Synopsys' Melissa Kirschner provides a primer on 5G and the five technologies that will need to work in tandem to bring the promised high speeds and low latency.... » read more

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