tag: Mentor

The Week In Review: Design
By Jesse Allen - 01 Dec, 2017 - Comments: 0

Tools Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors. IP Minima Processor revealed its dynamic-margining subsystem IP for near-threshold voltage design. The startup's hardware and software IP works with a CPU or DSP proc... » read more

How To Use CFD To Test And Analyze A Chip Package
By Prasad Tota - 30 Nov, 2017 - Comments: 0

By Prasad Tota and Robert Day Throughout the electronics industry, submicron feature size at the die level are driving package component sizes down to the design-rule level of the early technologies. Today’s integrated circuit (IC) package technology must deliver higher lead counts, reduced lead pitch, minimum footprint area, and significant volume reduction, which has led to semiconductor... » read more

Prototyping Partitioning Problems
By Ann Mutschler - 30 Nov, 2017 - Comments: 0

Gaps are widening in the prototyping of large, complex chips because the speed and capacity of the FPGA is not keeping pace with rapid rollout pace of advanced ASICs. This is a new twist for a well-established market. Indeed, prototyping with FPGAs is as old as the [gettech id="31071" t_name="FPGAs"] themselves. Even before they were called FPGAs, logic accelerators or LCAs (logic cell ar... » read more

Could Liquid IP Lead To Better Chips?
By Brian Bailey - 30 Nov, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

High-Performance 7nm IP Verification With The AFS Platform At Silicon Creations
By Mentor, a Siemens Business - 29 Nov, 2017 - Comments: 0

While there are many benefits to migrating to smaller process geometries, such as lower power and higher performance, the increased design complexity places an even higher burden on fast and efficient simulation technology. In addition, fast and accurate resistor/capacitor (RC) extraction is becoming increasingly important. Interconnect resistance is an increasing percentage of the total path r... » read more

Blog Review: Nov. 22
By Ed Sperling - 22 Nov, 2017 - Comments: 0

ARM's Jem Davies talks about an upcoming documentary on AI and where the lines need to be drawn between machine intelligence and human emotional intelligence. Mentor's Saunder Peng examines the impact of merging physical verification databases, which can cost time and resources, and how that can be streamlined. Cadence's Paul McClellan takes a look back at the Xerox Alto and how it change... » read more

Deals: Mentor-Solido, Marvell-Cavium
By Ed Sperling - 20 Nov, 2017 - Comments: 0

Marvell today signed a definitive agreement to buy Cavium for roughly $6 billion, ending weeks of speculation about whether the deal would go through. And Mentor, a Siemens business, paid an undisclosed price to buy Solido Design Automation, which tracks variation in complex designs. Both deals are part of a new flurry of M&A activity across the semiconductor industry as the industry ret... » read more

Move Data Or Process In Place? (Part 2)
By Brian Bailey - 20 Nov, 2017 - Comments: 0

Chip architectures, and even local system architectures, long have found that the best way to improve total system performance and power consumption is to move memory as close to processors as possible. This has led to cache architectures and memories that are tuned for those architectures, as discussed in part 1 of this article. But there are several tacit assumptions made in these architectur... » read more

The Week In Review: Design
By Jesse Allen - 17 Nov, 2017 - Comments: 0

Tools Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include improved performance when using code containing many inline randomized calls and up to 29% faster simulation speed of UVM. Pulsic added new features to its Unity Bus Planner for planning... » read more

Variation Spreads At 10/7nm
By Ed Sperling - 16 Nov, 2017 - Comments: 6

Variation between different manufacturing equipment is becoming increasingly troublesome as chipmakers push to 10/7nm and beyond. Process variation is a well-known phenomenon at advanced nodes. But some of that is actually due to variations in equipment—sometimes the exact same model from the same vendor. Normally this would fall well below the radar of the semiconductor industry. But as t... » read more

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