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32GT/s PCI Express Design Considerations


Today’s networking and rapidly emerging artificial intelligence (AI) applications are requiring more bandwidth in accelerators and GPUs, as well as faster interconnects to transmit and receive greater amounts of data. Towards the middle of 2017 the PCI-SIG industry consortium announced its latest specification, PCIe 5.0, which raised the data rate from 16GT/s to 32GT/s and doubled the link... » read more

The Week In Review: Design


Tools Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors. IP Minima Processor revealed its dynamic-margining subsystem IP for near-threshold voltage design. The startup's hardware and software IP works with a CPU or DSP proc... » read more

The Week In Review: Design


Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

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