tag: Samsung

OLED Displacing LCD, But Not Affecting Industry Leaders
By Michael Watts - 25 Jun, 2013 - Comments: 0

By Michael P.C. Watts One of the most common themes in high tech is how companies fail to deal with game-changing new products. Think about Kodak and digital cameras, Sony and the flash memory music player, Microsoft and the tablet, GE and Osram and the Light Emitting Diode (LED). The overwhelming conclusion seems to be that you have to be committed to making your own most valuable product red... » read more

Inside A 450mm Metrology Consortium
By Mark LaPedus - 20 Jun, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss 450mm metrology challenges with Menachem Shoval, a former manufacturing executive at Intel and chairman of the Metro450 consortium. The Israeli-based consortium is developing metrology technology for the next-generation, 450mm wafer size. The group consists of Intel, Applied Materials, Jordan Valley, Nanomotion, Nov... » read more

Consortium Mania Sweeps 450mm Landscape
By Mark LaPedus - 20 Jun, 2013 - Comments: 0

By Mark LaPedus In the mid-1990s, the semiconductor industry embarked on a costly and problematic migration from 200mm to 300mm wafer fabs. At the time, the 300mm development efforts were in the hands of two groups—Sematech and a Japanese-led entity. The equipment industry was on the outside looking in. And as a result, the migration from 200mm to 300mm fabs was out of sync and a nightma... » read more

3D-IC Testing With The Mentor Graphics Tessent Platform
By Various Writers - 20 Jun, 2013 - Comments: 0

Three-dimensional stacked integrated circuits (3D-ICs) are composed of multiple stacked die, and are viewed as critical in helping the semiconductor industry keep pace with Moore's Law. Current integration and interconnect methods include wirebond and flip-chip and have been in production for some time. 3D chips connected via interposers are in production at Xilinx, Samsung, IBM, and Sematec... » read more

VLSI Kyoto – The SOI Papers
By Various Writers - 19 Jun, 2013 - Comments: 0

By Adele Hars There were some breakthrough FD-SOI and other excellent SOI-based papers that came out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14, 2013). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both were presented in “Jumbo Joint Focus” sessions.  The papers should all b... » read more

Deja Vu All Over Again
By Brian Fuller - 19 Jun, 2013 - Comments: 0

By Brian Fuller I’m sure you’ve had that experience, at least once in your life, where you’re walking down the street, you pass someone and think, “Where do I know that guy from? Looks soooo familiar….” Well, here in this spot, I’m that guy. You’re looking at that incredibly sincere mug shot nearby and thinking, “Where do I know that guy from? Didn’t he sell me a really ... » read more

The Week In Review: June 7
By Ed Sperling - 07 Jun, 2013 - Comments: 0

By Ed Sperling For all the hesitation about moving the Design Automation Conference to Austin, it turns out that Austin has a lot of hardware engineers. In fact they flooded into the conference, turning it into one of the most successful in recent years and setting new records in multiple areas. Even Texas Gov. Rick Perry showed up to see what all the fuss was about. Mentor Graphics added c... » read more

Scaling The Lowly SRAM
By Mark LaPedus - 05 Jun, 2013 - Comments: 0

By Mark LaPedus Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one major challenge that is often overlooked in the equation—scaling the lowly static RAM (SRAM). In one key application, SRAM is the component used to make on-chip cache memories... » read more

3D NAND Market Heats Up
By Mark LaPedus - 16 May, 2013 - Comments: 0

By Mark LaPedus It’s the tale of two promising and separate 3D chip architectures. One technology is slowly taking root, while the other one is heating up. 3D stacked-die using through-silicon vias (TSVs) is on the slower path. Advanced chip-stacking has several challenges and is still a few years away from mass production. In contrast, 3D NAND is heating up, as Samsung and SK Hynix are a... » read more

Inside Leti’s Litho Lab
By Mark LaPedus - 16 May, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Serge Tedesco, lithography program manager at CEA-Leti; Laurent Pain, lithography lab manager at CEA-Leti; and Raluca Tiron, a senior scientist at CEA-Leti. SMD: CEA-Leti has two major and separate programs, including one in directed self-assembly (DSA) and another in multi-beam ... » read more

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