tag: Si2

The Week In Review: Design/IoT
By Jesse Allen - 27 Feb, 2015 - Comments: 0

Mergers & Acquisitions NXP acquired Quintic’s Bluetooth Low Energy and Wearable businesses, adding BLTE to their low power RF-connectivity portfolio. The team of approximately 65 is expected to join NXP when the deal closes in Q1 2015. Tools Cadence unveiled the integration of Forte's Cynthesizer with their own C-to-Silicon Compiler. The result is the Stratus high-level synthesis... » read more

Getting The Right Return On Invested Power Consumption
By Frank Schirrmeister - 26 Feb, 2015 - Comments: 0

Three weeks ago, I participated in a panel on low power and modeling at the system level. It took place at DesignCon 2015 in Santa Clara, together with representatives from AMD, Avago, and Qualcomm. Interestingly enough, it gave me the opportunity to set some of the myths and dis-information about power consumption in emulation straight, but more on that later. The panel was moderated by Steve ... » read more

Si2 Leadership Change
By Ann Mutschler - 03 Feb, 2015 - Comments: 0

Steve Schulz, who had been president and CEO of standards body Si2 for the past 12 years has resigned from the organization, Semiconductor Engineering learned today. He said he has thoroughly enjoyed the 12-1/2 years that he was with Si2 and is very, very proud of the successes from rebuilding it when he first joined and all of the growth the organization has had. “I still have a lot o... » read more

Unraveling Power Methodologies
By Brian Bailey - 15 Jan, 2015 - Comments: 0

When working on articles, the editors at Semiconductor Engineering sometimes hear things that make them stand back and question what seems to be an industry truth. One such statement happened last month while researching a different article. The statement was: Most designs are not top-down, but in fact bottom-up when it comes to power management. The most used methodology today is that the RTL... » read more

Important Changes Ahead
By Steve Schulz - 12 Jan, 2015 - Comments: 0

Two of Si2's important industry standards efforts will be featured later this month at DesignCon, a popular Silicon Valley event that is now in its 20th year. In the panel entitled, "System-Level Power Modeling—What's the Big Deal?", leading industry experts from AMD, Avago Technologies, Cadence, Docea Power, Qualcomm, and Si2 will focus on the growing need to take a higher level and more... » read more

Is The Stacked Die Ecosystem Stagnating?
By Ann Mutschler - 23 Dec, 2014 - Comments: 0

While the stacked die ecosystem in general is currently status quo, with not much happening in the past year, there is definitely work being done —albeit cautiously—on the design tools side of things. It would be easy to feel impatient that the design tools are not complete and available today for [getkc id="82" comment="2.5D"] and [getkc id="42" comment="3D IC"] implementation until hearin... » read more

Industry Scorecard For 2014
By Brian Bailey - 18 Dec, 2014 - Comments: 0

At the end of last year, Semiconductor Engineering asked the industry about the developments they expected to see in 2014. If you care to refresh your memory, they were categorized under markets, semiconductors and development tools. Now it is time to look back and see how accurate those predictions were and where they fell short. Markets The obvious trend, at the beginning of the year, wa... » read more

See The Internet Of Things…In 3D
By Steve Schulz - 05 Dec, 2014 - Comments: 0

No, you don’t need 3D glasses to experience two of the hottest emerging technology trends in electronics — just take advantage of the longest running conference series on the topic of 3-D integrated circuits. Now in its 11th year, the 3D Architectures for Semiconductor Integration and Packaging conference will take place in San Francisco next week. The event will feature two pre-conference ... » read more

The Internet Of Cores
By Brian Bailey - 20 Nov, 2014 - Comments: 0

Ever since the birth of the third-party [getkc id="43" comment="IP"] market, there has been a desire for plug-and-play compatibility between cores. Part of the value proposition of reuse is that a block has been used before, and has been verified and validated by having been implemented in silicon. By re-using the core, many of these tasks no longer land on the [getkc id="81" kc_name="SoC"] dev... » read more

The Week In Review: Design
By Ed Sperling - 24 Oct, 2014 - Comments: 0

IP Cadence rolled out a portfolio of stacked die memory verification IP to support Wide I/O-2, Hybrid Memory Cube, high-bandwidth memory, and DDR4-3DS. Included are direct memory access for read, write, save, preload and comparison of memory contents, assertions, error configurability, and a built-in address manager. ARM rolled out additions to its enterprise-class SoC interconnects for qua... » read more

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