Chiplets For The Masses


Chiplets are a compelling technology, but so far they are available only to a select few players in the industry. That's changing, and the industry has taken little steps to get there, but timing for when you will be able to buy a chiplet to integrate into your system remains uncertain. While new fabrication nodes continue to be developed, scaling is coming to an end, be it for physical or e... » read more

4 Horsemen Of Wire Harness Manufacturing


Growing demands for automotive electrical and electronic (E/E) features drive increased complexity in the wiring harnesses that carry power and data signals to components around the vehicle. As a result, the wire harness manufacturing industry is expected to see significant growth, expanding into a 91 billion dollar industry in 2025. However, wire harness manufacturers often operate on small pr... » read more

Firmware Skills Shortage


Good hardware without good software is a waste of silicon, but with so many new processors and accelerator architectures being created, and so many new skills required, companies are finding it hard to hire enough engineers with low-level software expertise to satisfy the demand. Writing compilers, mappers and optimization software does not have the same level of pizazz as developing new AI ... » read more

Advancing IC And Systems Design With The Digital Twin


As many of you may have seen, we’ve passed a major milestone since Siemens announced its intent to acquire Mentor Graphics four years ago. As of January 1, 2021, “Mentor, a Siemens business” has become “Siemens EDA” and remains a segment of the larger Siemens Digital Industries Software organization. Siemens is bringing together one of the world’s most comprehensive EDA portfolios w... » read more

When Is Verification Done?


Even with the billions of dollars spent on R&D for EDA tools, and tens of billions more on verification labor, only 30% to 50% of ASIC designs are first time right, according to Wilson Research Group and Siemens EDA. Even then, these designs still have bugs. They’re just not catastrophic enough to cause a re-spin. This means more efficient verification is needed. Until then, verificati... » read more

Big Challenges In Verifying Cyber-Physical Systems


Semiconductor Engineering sat down to discuss cyber-physical systems and how to verify them with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Maillet-Contoz, system and architect specialist at STMicroelectronics. This discussion was... » read more

Surviving The Three Phases Of High Density Advanced Packaging Design


The growth of High Density Advanced Packages (HDAP) such as FOWLP, CoWoS, and WoW is triggering a convergence of the traditional IC design and IC package-design worlds. To handle these various substrate scenarios, process transformation must occur. This paper discusses the three phases of HDAP design and provides tips on how to survive their challenges. To read more, click here. » read more

Blog Review: Feb. 24


Siemens EDA's Harry Foster checks out the efficiency and effectiveness of verification on ASIC and IC designs with a look at how many projects meet the original schedule, the number of required spins, and classification of functional bugs. Cadence's Paul McLellan listens in as Philippe Magarshack of ST Microelectronics on how the company uses massive amounts of data generated by its fabs to ... » read more

Blog Review: Feb. 17


In a video, Synopsys' Tim Mackey warns that IoT device manufacturers are dealing with a serious challenge when it comes to security and points to the types of software threats that could impact IoT products. Siemens' Paul van Straten finds that the rise in vehicle complexity and intensified global competition means traditional automotive OEMs will need to explore new approaches to vehicle de... » read more

Design For Reliability


Circuit aging is emerging as a mandatory design concern across a swath of end markets, particularly in markets where advanced-node chips are expected to last for more than a few years. Some chipmakers view this as a competitive opportunity, but others are unsure we fully understand how those devices will age. Aging is the latest in a long list of issues being pushed further left in the desig... » read more

← Older posts Newer posts →