tag: Siemens EDA

Hybrid Verification: The Only Way Forward
By Brian Bailey - 15 Dec, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="10" kc_name=" functional verification"]. The inability of RTL [getkc id="11" kc_name="simulation"] to keep up with verification needs is causing rapid change in the industry. Taking part in the discussion are Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Janick Bergeron, fe... » read more

Week 27: Announcing DAC TV
By Anne Cirkel - 12 Dec, 2014 - Comments: 1

I’m just back from a few days in San Jose, which luckily is only a short flight away from Portland. After so many of these trips I've found that most of the time I'm surrounded by familiar faces and the one or two flustered employees that couldn’t catch their much more convenient corporate commuter flight. I have to admit the idea of bypassing airport security and just showing my badge, gra... » read more

The Week In Review: Design/IoT
By Ed Sperling - 12 Dec, 2014 - Comments: 0

Tools Cadence rolled out a use-case scenario verification tool that automates some test development that has been done manually in the past. The new tool accelerates development of software-driven tests and debug to ferret out complex SoC-level bugs. Cadence claims a 10X productivity improvement. Mentor Graphics uncorked a new version of its verification IP for PCI Express. The new IP decre... » read more

Yield Ramp Challenges Increase
By Ann Mutschler - 11 Dec, 2014 - Comments: 0

As semiconductor manufacturing moves down to smaller process nodes, there’s no doubt that it is increasingly difficult to ramp both test and manufacturing yields. One reason for this is simply scale. Smaller nodes translate into more steps and greater complexity in the manufacturing process, with attendant process variations. “Smaller process nodes increase the amount of embedded mem... » read more

Eight Steps For Ensuring PCB Assembly Success
By Mentor, a Siemens Business - 11 Dec, 2014 - Comments: 0

So, you have invented and designed the next hit product, poised to wreak havoc with the competition and ensure continued financial success for the company for a long time into the future. Guess what though; the job is not done until the product hits the street. In between design and sales is printed circuit board (PCB) manufacturing and assembly. All critical business metrics, including, cos... » read more

Multiple Patterns, Multiple Trade-Offs
By David Abercrombie - 11 Dec, 2014 - Comments: 0

As the saying goes, “There is no such thing as a free lunch.” That is a reality that chip designers have had to live by from the beginning. From the advent of the first design rule, it was clear that you couldn’t just do anything you wanted. In the end, everything comes down to trade-offs. Whether it’s area, speed, leakage, noise sensitivity, or drive current, doing something to impr... » read more

Blog Review: Dec. 10
By Ed Sperling - 10 Dec, 2014 - Comments: 1

ARM's Brad Nemire takes a look at a variety of the latest smart devices. Check out the intelligent frying pan that tells you the temperature, the amount of time needed to cook something, and when it's done. Check out the "Homey," too. You can now give verbal commands to your home. Just don't tell it to roll over. Who needs paper? Or more accurately, who needs more than one sheet of paper—e... » read more

Security Risks Grow Worse
By Ed Sperling - 09 Dec, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss security issues for connected devices with Marc Canel, vice president of security at [getentity id="22186" comment="ARM"]; Paul Kocher, president and chief scientist for the Cryptography Research division of [getentity id="22671" e_name="Rambus"]; Michael Poitner, global segment marketing manager at [getentity id="22499" e_name="NXP"]; Felix Baum, h... » read more

Top-down Design Of Distributed Embedded Systems In Light Of Timing Considerations
By Mentor, a Siemens Business - 09 Dec, 2014 - Comments: 0

Proper safeguarding of safety-critical systems in an automotive environment cannot be ensured sufficiently without taking timing into consideration. The failure to observe timing constraints can lead to malfunctions and, in a worst-case scenario, can cause vehicle damage and personal injury. AUTOSAR 4.0 now supports timing constraints, but the standard, although very powerful, still is not able... » read more

The Week In Review: Design/IoT
By Ed Sperling - 05 Dec, 2014 - Comments: 0

Tools Calypto rolled out its third-generation high-level synthesis platform after three years of development, adding granular control over which regions are optimized and the ability to work top-down and bottom-up—basically allowing designers to zoom in and out as needed. In addition, the tool has a 10X increase in capacity and supports SystemC and C++. eSilicon unveiled its online conf... » read more

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