tag: Siemens EDA

To Cut or Not To Cut? That is the Double Patterning Question
By David Abercrombie - 14 Dec, 2011 - Comments: 1

By David Abercrombie The challenges of double pattering (DP)-based design are looming large to those customers starting to move to the 20 nm technology node. Of course, much of the fear and trepidation is simply due to it being something new to learn, and the sense of risk that a move into the unknown can instill. Regardless of emotions involved, DP does place new restrictions on physical la... » read more

Experts At The Table: Stacked Die And The Supply Chain
By Ed Sperling - 13 Dec, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis ... » read more

Experts At The Table: Stacked Die And The Supply Chain
By Ed Sperling - 05 Dec, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis ... » read more

Energy Vs. Power: Energy, Power Optimization Is A System-Level Challenge
By Ed Sperling - 01 Dec, 2011 - Comments: 0

By Ann Steffora Mutschler Power issues today, whether they are related to low power in a smart phone or highly efficient power for data center applications, are so pervasive that they touch the entire design team—and must be carefully prioritized at the system or architectural level. As discussed in Part 1 of this series, energy and power are different entities and must be understood dist... » read more

Speed Demons
By Barry Pangrle - 01 Dec, 2011 - Comments: 0

By Barry Pangrle For extreme world record performance levels, the required power levels are also typically extreme. It’s that age-old battle against diminishing returns to squeeze out every last drop of performance versus practical limits and wallets. For example, a top fuel dragster can consume about six gallons of fuel for a quarter-mile run down the strip. As has previously been shown ... » read more

Playing The Voltage Game
By Ed Sperling - 01 Dec, 2011 - Comments: 0

y Ed Sperling Scaling down the voltage to boost battery life and cut energy costs has always been considered the best option, but it’s getting more difficult at advanced nodes and in stacked die packages. The key problems are noise and leakage. Lowering the voltage exacerbates both of them, forcing a rethinking of the whole design process starting at the architectural level and continuing... » read more

Experts At The Table: Stacked Die And The Supply Chain
By Ed Sperling - 26 Nov, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis... » read more

Build It Faster
By Ed Sperling - 17 Nov, 2011 - Comments: 0

By Ed Sperling Hitting market windows with IC designs has always been a struggle, but the race to the finish line is becoming more critical—and much more difficult. The reason: Market windows themselves are shrinking. Products that used to stick around for years may now only last for months, replaced by newer versions that offer either better performance or lower power. In many cases, par... » read more

Dinner Talk
By Jon McDonald - 17 Nov, 2011 - Comments: 0

By Jon McDonald Recently at dinner we were discussing a new video game my son wanted. My wife and I were less than thrilled with the game due to some of the adult themes I had seen in the reviews. As my son was trying to convince us that it was an acceptable game he fell back on the old standard justification: “All my friends are playing it!” This is one of the poorest reasons for anyt... » read more

CMP, ST et al offer 28nm FD-SOI for prototyping, research
By Various Writers - 06 Nov, 2011 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ What would a port to 28nm FD-SOI do for your design?  A recent announcement by CMP, STMicroelectronics and Soitec invites you to find out.  Specifically, ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process – which uses innovative silicon substrates from Soitec and incorporates robust, compact model... » read more

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