tag: Siemens EDA

Power To Fly
By Barry Pangrle - 04 Nov, 2010 - Comments: 0

By Barry Pangrle As technologies mature, they often follow similar profiles. Back on Oct. 14th I heard Lesley Curwen of the BBC interviewing Charles Champion, executive vice president of engineering at Airbus. Champion said that over the last 40 years the airline industry has reduced emissions and fuel burn by 70%. He pointed out that the industry initially focused on speed and the tendency no... » read more

The Trouble With Low-Power Verification
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ed Sperling If verification accounts for 70% of the non-recurring engineering expenses in a design, what percentage does verifying a low-power design actually consume? Answer: No one knows for sure. The reason has more to do with insufficient data than tools, processes or flows. That’s also the reason that power models have never been created for more than a single design. “Power... » read more

Power-Delivery Network Challenges Grow
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler Physics is forcing convergence in the SoC power delivery network, whose job is to ensure that every device on a chip has a robust and stable voltage so it can meet its expected functionality and timing. In the past, chip design, package design and board design were separate disciplines, guard-banded to ensure that all the parts worked well together. Today, given t... » read more

Making Software More Efficient
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ed Sperling Software is being targeted by most of the major chip vendors and EDA companies as the next big opportunity for saving power, but exactly which software should be modified and by whom isn’t always clear. To some extent those answers depend upon which part of the software stack vendors or engineers believe can be adjusted most easily, and so far there is no widespread agreeme... » read more

Best Practices For Multicore SoC Test And Debug
By Ann Mutschler - 21 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler In increasingly complex SoC designs, many of which contain multiple cores and multiple modes, determining best practices for testing and debugging is a moving target. Jason Andrews, architect at Cadence Design Systems, said multicore debug is a huge issue. It isn’t easy to do, and there aren’t many good ways to do it. He suggested one approach is to try to u... » read more

The Growing Need For Concurrent Design
By Ed Sperling - 21 Oct, 2010 - Comments: 0

By Ed Sperling The move toward concurrent design is escalating at advanced nodes, driven more by the need to ensure that everything works than previous efforts aimed at efficiency and time-to-market. While the concept has surfaced before in limited doses—engineers and EDA companies have been talking about doing more things simultaneously for the better part of a decade—there are some in... » read more

The Future Of 3D Stacking
By Ed Sperling - 21 Oct, 2010 - Comments: 0

By Ed Sperling Despite concerns about the lack of tools, an unstable process, questionable interconnects, thermal overloads and electrostatic discharge, 3D stacking appears to be making headway. At the very least, lots of companies of all sizes are betting heavily that it will succeed. The first wave, which is expected to start showing up late next year, will likely come from a handful of t... » read more

Bridging IP With Verification Standards
By Ann Mutschler - 21 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler Standards body Accellera is sounding the gong to summon all verification IP providers to check out its efforts in connection with IP-XACT -- IEEE 1685, "Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows” – with verification IP. The IP-XACT technical committee has been busy over the past year. Formerly an effor... » read more

ESL’s Effect On What Engineers Assume
By Jon McDonald - 21 Oct, 2010 - Comments: 0

By Jon McDonald I’m on a cruise this week. I’m spending some time thinking about things other than work, but from time to time even normal life does have an impact on esoterically engineering concepts. As the cruise has visited a number of different ports my wife and I have made many assumptions—assumptions about what we both want to do in port, assumptions about what will be availabl... » read more

The Good Kind Of Bias
By Barry Pangrle - 07 Oct, 2010 - Comments: 1

By Barry Pangrle Back gating, body bias, substrate bias, and back bias all refer to a technique for dynamically adjusting the threshold voltage of a CMOS transistor. CMOS transistors are often thought of as three-terminal devices with terminals for the source, gate and drain. It’s quite common, though, to have a fourth terminal available connected to the substrate (or body). Most engineer... » read more

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