tag: Siemens

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 17 Aug, 2018 - Comments: 0

Cybersecurity Check Point Software Technologies reports that facsimile machines (yes, people still use them!) can be subject to hacking through vulnerabilities in their communication protocols. The HP Officejet Pro All-in-One fax printers and other fax machines can be compromised with a hacker only knowing a fax number, according to the company. Check Point Research says a design flaw in Andro... » read more

Blog Review: Aug. 15
By Jesse Allen - 15 Aug, 2018 - Comments: 0

Cadence's Paul McLellan checks out what's driving the growth of China's semiconductor industry plus the state of fab construction, from a CAPSA presentation by SEMI's Lung Chu. Mentor's Joe Hupcey III has some tips for how to handle inconclusive results in formal verification, starting with how to identify where the analysis got stuck. Synopsys' Taylor Armerding listens in on a presentati... » read more

Do Parallel Tools Make Sense?
By Brian Bailey - 10 Aug, 2018 - Comments: 0

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 10 Aug, 2018 - Comments: 0

Cybersecurity Jens (Atom) Steube, a cybersecurity researcher and creator of the Hashcat password cracking tool, was probing for vulnerabilities in the new WPA3 security standard for Wi-Fi routers. WPA3 presents a robust defense against hacking, yet Steube discovered a security flaw in routers using WPA/WPA2 – one that leaves Wi-Fi passwords enabled with Pairwise Master Key Identifiers vulner... » read more

Week In Review: Design, Low Power
By Jesse Allen - 10 Aug, 2018 - Comments: 0

Achronix and Mentor uncorked an optimized HLS flow for Achronix's FPGA technology products. The integrated development environment enables designers to quickly go from C++ to FPGA using Mentor's Catapult HLS and Achronix's ACE design tools. Initially used for 5G wireless applications to reduce the overall development effort and improve QoR, it is suitable for any design targeting Achronix techn... » read more

Chip Aging Becomes Design Problem
By Brian Bailey - 09 Aug, 2018 - Comments: 9

Chip aging is a growing problem at advanced nodes, but so far most design teams have not had to deal with it. That will change significantly as new reliability requirements roll out across markets such as automotive, which require a complete analysis of factors that affect aging. Understanding the underlying physics is critical, because it can lead to unexpected results and vulnerabilities. ... » read more

Updated UVM Cookbook Supports IEEE 1800.2 Standard And Emulation
By Tom Fitzpatrick - 09 Aug, 2018 - Comments: 0

I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here. Cookbook Overview Diagram The Universal Verification Methodology (UVM) is a standard library of SystemVerilog classes that supports a modular, reusable testbench architecture for constrained-random functional verification. Meanwhile, Mentor’... » read more

Utilizing Clock-Gating Efficiency To Reduce Power In RTL Designs
By Mentor, a Siemens Business - 08 Aug, 2018 - Comments: 0

With the advent of the consumer era and the popularity of mobile applications, power optimization is the mantra of the day. Designers go through several iterations to optimize power in order to achieve their power budgets. The average Clock-Gating Efficiency for a design is a much better indicator of dynamic power consumption because it is a measure of both how many and how long registers are g... » read more

Blog Review: Aug. 8
By Jesse Allen - 08 Aug, 2018 - Comments: 0

Cadence's Meera Collier provides a primer on the basics of quantum computing, including how quantum gates work using superpositions and how it could impact chip design. Mentor's Dennis Brophy shares a list of resources to help you get up to speed on the recently-approved Portable Test and Stimulus standard, which enables test scenarios to be run across different execution platforms. Synop... » read more

The Chiplet Race Begins
By Mark LaPedus - 06 Aug, 2018 - Comments: 1

Momentum is building for the development of advanced packages and systems using so-called chiplets, but the technology faces some challenges in the market. A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system. In fact, the Defense Advanced Research Projects Agency (DARPA), part... » read more

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