tag: Siemens

Creating Software Separation For Mixed Criticality Systems
By Mentor, a Siemens Business - 20 Dec, 2017 - Comments: 0

The continued evolution of powerful embedded processors is enabling more functionality to be consolidated into single heterogeneous multicore devices. Mixed criticality designs, those designs which contain both safety-critical and non-safety critical processes, can successfully leverage these devices and meet the regulatory requirements for IEC safety standards and the highest level of ISO. Thi... » read more

The Trouble With Models
By Ed Sperling - 20 Dec, 2017 - Comments: 0

Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be dozens of models required for complex SoCs. Some are ... » read more

Blog Review: Dec. 20
By Jesse Allen - 20 Dec, 2017 - Comments: 0

Mentor's Andrew Macleod points out five things that need to happen for autonomous and electric cars to move from R&D and test cases to mass-produced, commercially viable vehicles. Synopsys' Iain Singleton provides some tips on tackling large designs with formal and how the assume-guarantee technique helps split them without masking bugs. Cadence's Paul McLellan shares updates from the... » read more

The Week In Review: Design
By Jesse Allen - 15 Dec, 2017 - Comments: 0

M&A Synopsys finalized its acquisition of Black Duck Software, which provides software for managing and securing open source software in projects, adding to Synopsys' burgeoning software analysis and security business. The cash deal was approximately $547 million net of cash acquired. STMicroelectronics acquired Atollic, maker of the Eclipse-based TrueSTUDIO Integrated Development Envir... » read more

Co-Modeling Takes Emulation To The Next Level: System-Of-Systems
By Ron Squiers - 14 Dec, 2017 - Comments: 0

As designs move beyond System-on-Chip (SoC) to more complex System-of-Systems (SoS), it’s essential for design teams to effectively verify that these systems function together as intended. Increasingly, system design companies are turning to emulators as the only verification platform with the capacity and performance to validate that their SoC and SoS designs function as intended. Today�... » read more

Accounting For Power Earlier
By Ann Mutschler - 14 Dec, 2017 - Comments: 5

Concerns about power usage in an SoC are far from new, but the adoption of power management techniques still varies by company and by project. Leading semiconductor providers have made the necessary changes in tooling and methodology to account for [getkc id="106" kc_name="power awareness"] because they have to, but the rest of the industry hasn't necessarily caught up. “The companies t... » read more

EDA Challenges Machine Learning
By Brian Bailey - 14 Dec, 2017 - Comments: 1

Over the past few years, [getkc id="305" kc_name="machine learning"] (ML) has evolved from an interesting new approach that allows computers to beat champions at chess and Go, into one that is touted as a panacea for almost everything. While there is clearly a lot of hype surrounding this, it appears that machine learning can produce a better outcome for many tasks in the EDA flow than even the... » read more

Co-modeling: A Powerful Capability For Hardware Emulation
By Mentor, a Siemens Business - 13 Dec, 2017 - Comments: 0

Understanding co-modeling technology, its impact on verification and validation should be a critical aim for anyone selecting and deploying emulation co-modeling resources. This paper explores how emulation co-modeling — specifically for the Veloce Strato emulation platform from Mentor, a Siemens business — is architected to meet the needs of advanced verification and validation. To rea... » read more

Blog Review: Dec. 13
By Jesse Allen - 13 Dec, 2017 - Comments: 0

Mentor's Sherif Hany notes that pattern matching isn't just for litho hotspots anymore, and is increasingly being used in a wide range of early design phase checks, DRC flows, layout retargeting and fixing and DFM checks. Synopsys' Eric Huang explains why USB cables have gotten so short, even though no length is mentioned in the specification. Cadence's Paul McLellan listens in as Jeremy ... » read more

Could Liquid IP Lead To Better Chips?
By Brian Bailey - 13 Dec, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy