tag: Siemens

How To Sleep Easier If You Test Auto ICs For A Living
By Andrew Macleod - 07 Dec, 2017 - Comments: 0

Last month, I looked at the product definition process of automotive ICs, using the $7 billion microcontroller market as an illustration of design exploration to optimize performance, features, die size and product cost. Now I’d like to look at the back end of the process — the final IC testing that’s still critical no matter how sound the upfront work in defining a featuring set and aptl... » read more

Preventing IoT Edge Device Vulnerabilities
By Mentor, a Siemens Business - 07 Dec, 2017 - Comments: 0

As an EDA toolchain provider, Mentor keeps a close eye on security issues that occur in the world of electronics. We see volumes of research centered on protecting complex SoCs from attacks and interesting studies about detecting malicious logic in these ICs. But, security issues around IoT edge devices are rarely mentioned in the literature. However, the projected billions of IoT edge devices ... » read more

Enabling Automotive Design
By Ann Mutschler - 07 Dec, 2017 - Comments: 0

Falling automotive electronics prices, propelled by advances in chip manufacturing and innovations on the design side, are driving a whole new level of demand across the automotive industry. Innovations that were introduced at the luxury end of the car market over the past couple years already are being implemented in more standard vehicles. The single biggest driver of change in the automo... » read more

State Of The IoT
By Jeff Dorsch - 06 Dec, 2017 - Comments: 1

The Internet of Things represents many things to many people, and many of them are not good. For some it is either a laughingstock or a punching bag. For IT, it is a subject of derision because securing all connected devices at the edge is a nightmare. But in all cases, the general consensus is that the IoT has failed to live up to expectations and a level of hype not seen since the dot-com ... » read more

Blog Review: Dec. 6
By Jesse Allen - 06 Dec, 2017 - Comments: 0

Synopsys' Eric Huang examines electromagnetic interference, the Bit Error Rate in USB 3.2 and how different transfer types handle errors. Mentor's Nitin Bhagwath points out several things that can cause DDR signals to behave badly, from excessive ringing to stubs in the channel. Cadence's Paul McLellan listens in as Oski CEO Vigyan Singhal explains the basics of assertion-based verificati... » read more

Which Verification Engine? (Part 2)
By Ed Sperling - 06 Dec, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

Big Challenges, Changes For Debug
By Ann Mutschler - 04 Dec, 2017 - Comments: 1

By Ann Steffora Mutschler & Ed Sperling Debugging a chip always has been difficult, but the problem is getting worse at 7nm and 5nm. The number of corner cases is exploding as complexity rises, and some bugs are not even on anyone's radar until well after devices are already in use by end customers. An estimated 39% of verification engineering time is spent on debugging activities the... » read more

The Week In Review: Design
By Jesse Allen - 01 Dec, 2017 - Comments: 0

Tools Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors. IP Minima Processor revealed its dynamic-margining subsystem IP for near-threshold voltage design. The startup's hardware and software IP works with a CPU or DSP proc... » read more

How To Use CFD To Test And Analyze A Chip Package
By Prasad Tota - 30 Nov, 2017 - Comments: 0

By Prasad Tota and Robert Day Throughout the electronics industry, submicron feature size at the die level are driving package component sizes down to the design-rule level of the early technologies. Today’s integrated circuit (IC) package technology must deliver higher lead counts, reduced lead pitch, minimum footprint area, and significant volume reduction, which has led to semiconductor... » read more

Prototyping Partitioning Problems
By Ann Mutschler - 30 Nov, 2017 - Comments: 0

Gaps are widening in the prototyping of large, complex chips because the speed and capacity of the FPGA is not keeping pace with rapid rollout pace of advanced ASICs. This is a new twist for a well-established market. Indeed, prototyping with FPGAs is as old as the [gettech id="31071" t_name="FPGAs"] themselves. Even before they were called FPGAs, logic accelerators or LCAs (logic cell ar... » read more

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