Week In Review: Auto, Security, Pervasive Computing


An effort to fund U.S. science and technology initiatives with at least $100 billion is getting a thumbs up from the SIA (Semiconductor Industry Association). The Endless Frontier Act —  a bipartisan, bicameral bill introduced on Thursday in the U.S. House of Representatives — will invest money into semiconductor research and development and other related fields such as material science, q... » read more

What’s So Important About Processor Extensibility?


While the ability to extend a processor is nothing new, market dynamics are forcing a growing percentage of the industry to consider it a necessary part of their product innovation. From small IoT functions to massive data centers and artificial intelligence, the need to create an optimized processing platform is often the only way to get more performance or lower power out of the silicon area ... » read more

FPGA Prototyping Complexity Rising


Multi-FPGA prototyping of ASIC and SoC designs allows verification teams to achieve the highest clock rates among emulation techniques, but setting up the design for prototyping is complicated and challenging. This is where machine learning and other new approaches are beginning to help. The underlying problem is that designs are becoming so large and complex that they have to be partitioned... » read more

The Seven Steps Of Formal Signoff


“Signoff” may be the most exciting—and frightening—word in semiconductor development. After many months, or even years of team effort, committing a design to silicon fabrication is indeed an exciting and rewarding event. But, there’s often significant anxiety involved as well – if any missed issues result in having to “turn” the chip, the increased costs and time-to-market delay... » read more

RTL Architect: Simply Better RTL


Electronic devices play a key role in society. They connect us to one another through voice, video and chat. They entertain, educate, protect and heal us in new and ever-expanding ways. They have changed the way we work, live and play. Silicon chips are the fast beating heart (2 to 3 billion beats per second) of these devices. For decades, the relentless advancements in semiconductor process te... » read more

Blog Review: May 27


Mentor's Neil Johnson takes a look at achieving a practical verification methodology starting with an exclusively constrained random flow and building up by adding techniques and gauging the consequences. Cadence's Paul McLellan explains the history of neural networks and how we've been trying to mimic the brain for decades, only to see funding dry up until a sudden resurgence of annotated i... » read more

Week In Review: Design, Low Power


Tools & IP Cadence unveiled ten two verification IP (VIP) to support hyperscale data centers, automotive, and consumer and mobile applications. The new VIPs include complete bus functional models, integrated protocol checks and coverage models, and a specification-compliant verification plan. The VIPs cover CXL, HBM3, Ethernet 802.3ck, CSI-2 3.0, MIPI I3C 1.1, TileLink, eUSB2, UFS 3.1, MIP... » read more

Blog Review: May 20


Synopsys' Jonathan Knudsen demystifies fuzzing techniques and why the process of sending targeted, intentionally invalid data is important to determining security. Mentor's Chris Spear explains both the potential benefits and challenges of the UVM Configuration Database and guidelines to improve performance. Cadence's Paul McLellan continues the look back at mobile history with the beginn... » read more

Design For Narrowband IoT


Most low-power chips are designed with the assumption that batteries can be recharged or replaced, but there is a whole set of IoT devices under development that are expected to be always-on, communicate over a cellular infrastructure, and remain functional on a coin-sized lithium-ion battery for a decade or more. Welcome to the world of Narrowband IoT (NB-IoT), a 3GPP standard (also known a... » read more

Rising Packaging Complexity


Synopsys’ Rita Horner looks at the design side of advanced packaging, including how tools are chosen today, what considerations are needed for integrating IP while maintaining low latency and low power, why this is more complex in some ways than even the most advanced planar chip designs, and what’s still missing from the tool flow. » read more

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